def : MnemonicAlias<"shaddsubx", "shasx">;
// SHSAX == SHSUBADDX
def : MnemonicAlias<"shsubaddx", "shsax">;
+// SSAX == SSUBADDX
+def : MnemonicAlias<"ssubaddx", "ssax">;
// LDRSBT/LDRHT/LDRSHT post-index offset if optional.
// Note that the write-back output register is a dummy operand for MC (it's
@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x25,0xf3,0x0f,0x03]
+@------------------------------------------------------------------------------
+@ SSAX
+@------------------------------------------------------------------------------
+ ssubaddx r2, r3, r4
+ it lt
+ ssubaddxlt r2, r3, r4
+ ssax r2, r3, r4
+ it lt
+ ssaxlt r2, r3, r4
+
+@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: it lt @ encoding: [0xb8,0xbf]
+@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: it lt @ encoding: [0xb8,0xbf]
+@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
+
+
@------------------------------------------------------------------------------
@ SUB (register)
@------------------------------------------------------------------------------