if (type->isFloatTy())
weight = CW_Register;
break;
+ case 'I': // signed 16 bit immediate
+ if (isa<ConstantInt>(CallOperandVal))
+ weight = CW_Constant;
+ break;
}
return weight;
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
+ std::string &Constraint,
+ std::vector<SDValue>&Ops,
+ SelectionDAG &DAG) const {
+ SDValue Result(0, 0);
+
+ // Only support length 1 constraints for now.
+ if (Constraint.length() > 1) return;
+
+ char ConstraintLetter = Constraint[0];
+ switch (ConstraintLetter) {
+ default: break; // This will fall through to the generic implementation
+ case 'I': // Signed 16 bit constant
+ // If this fails, the parent routine will give an error
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+ EVT Type = Op.getValueType();
+ int64_t Val = C->getSExtValue();
+ if (isInt<16>(Val)) {
+ Result = DAG.getTargetConstant(Val, Type);
+ break;
+ }
+ }
+ return;
+ }
+
+ if (Result.getNode()) {
+ Ops.push_back(Result);
+ return;
+ }
+
+ TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
+}
+
bool
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The Mips target isn't yet aware of offsets.
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
+ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+ /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
+ /// true it means one of the asm constraint of the inline asm instruction
+ /// being processed is 'm'.
+ virtual void LowerAsmOperandForConstraint(SDValue Op,
+ std::string &Constraint,
+ std::vector<SDValue> &Ops,
+ SelectionDAG &DAG) const;
+
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
/// isFPImmLegal - Returns true if the target can instruction select the
--- /dev/null
+;
+;This is a negative test. The constant value given for the constraint
+;is greater than 16 bits.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
+ tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind
+ ret i32 0
+}
+
--- /dev/null
+;
+; Register constraint "r" shouldn't take long long unless
+; The target is 64 bit.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+; r with long long
+;CHECK-ERRORS: error: couldn't allocate output register for constraint 'r'
+
+ tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
+ ret i32 0
+}
+
--- /dev/null
+; Positive test for inline register constraints
+;
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+define i32 @main() nounwind {
+entry:
+
+; r with char
+;CHECK: #APP
+;CHECK: addi ${{[0-9]+}},${{[0-9]+}},23
+;CHECK: #NO_APP
+ tail call i8 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
+
+; r with short
+;CHECK: #APP
+;CHECK: addi ${{[0-9]+}},${{[0-9]+}},13
+;CHECK: #NO_APP
+ tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
+
+; r with int
+;CHECK: #APP
+;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK: #NO_APP
+ tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
+
+ ret i32 0
+}
--- /dev/null
+;
+; Register constraint "r" shouldn't take long long unless
+; The target is 64 bit.
+;
+;
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+
+
+define i32 @main() nounwind {
+entry:
+
+
+; r with long long
+;CHECK: #APP
+;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK: #NO_APP
+ tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
+ ret i32 0
+}
+
--- /dev/null
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+define i32 @main() nounwind {
+entry:
+
+; First I with short
+; CHECK: #APP
+; CHECK: addi $3,$2,4096
+; CHECK: #NO_APP
+ tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
+
+; Then I with int
+; CHECK: #APP
+; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3
+; CHECK: #NO_APP
+ tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
+
+ ret i32 0
+}
+