}
// Condition code registers.
-def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
+def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]> {
+ let isAllocatable = 0;
+}
// for transforming FPn allocations to STn registers)
def RST : RegisterClass<"X86", [f80, f64, f32], 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- RSTClass::iterator
- RSTClass::allocation_order_end(const MachineFunction &MF) const {
- return begin();
- }
- }];
+ let isAllocatable = 0;
}
// Generic vector registers: VR64 and VR128.
// Status flags registers.
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
let CopyCost = -1; // Don't allow copying of status registers.
-
- // EFLAGS is not allocatable.
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- CCRClass::iterator
- CCRClass::allocation_order_end(const MachineFunction &MF) const {
- return allocation_order_begin(MF);
- }
- }];
+ let isAllocatable = 0;
}
}];
}
-def RRegs : RegisterClass<"XCore", [i32], 32,
- // Reserved
- [CP, DP, SP, LR]> {
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- RRegsClass::iterator
- RRegsClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- RRegsClass::iterator
- RRegsClass::allocation_order_end(const MachineFunction &MF) const {
- // No allocatable registers
- return begin();
- }
- }];
+// Reserved
+def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> {
+ let isAllocatable = 0;
}