When lowering an inreg sext first shift left, then right arithmetically.

Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 2dade85832620ff146baff8db9a60f8a69881faa..3989295ff595ec02086f63eafa5e78548914aa74 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -508,9 +508,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
   EVT VT = Op.getValueType();
 
-  // Make sure that the SRA and SRL instructions are available.
+  // Make sure that the SRA and SHL instructions are available.
   if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
-      TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
+      TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
     return DAG.UnrollVectorOp(Op.getNode());
 
   DebugLoc DL = Op.getDebugLoc();
@@ -521,7 +521,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
   SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
 
   Op = Op.getOperand(0);
-  Op =   DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz);
+  Op =   DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
   return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
 }
 

diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll
index 42334d7030d984f34b222d26a3de70c471f9a17d..998645d90da62df5cfc92eb8abc8f4d00a0a9ecb 100644 (file)
--- a/test/CodeGen/PowerPC/vec_extload.ll
+++ b/test/CodeGen/PowerPC/vec_extload.ll
@@ -15,7 +15,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
   ret <16 x i8> %c
 }
 ; CHECK: v16si8_sext_in_reg:
-; CHECK: vsrb
+; CHECK: vslb
 ; CHECK: vsrab
 ; CHECK: blr 
 
@@ -37,7 +37,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
   ret <8 x i16> %c
 }
 ; CHECK: v8si16_sext_in_reg:
-; CHECK: vsrh
+; CHECK: vslh
 ; CHECK: vsrah
 ; CHECK: blr 
 
@@ -61,7 +61,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
   ret <4 x i32> %c
 }
 ; CHECK: v4si32_sext_in_reg:
-; CHECK: vsrw
+; CHECK: vslw
 ; CHECK: vsraw
 ; CHECK: blr