Add some more comments about checkings of invalid register numbers.

And two test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index bc0ba92d58e22bd89be2774e23b2b7282d219d93..f4fa3de268456b30e693244a5eda4b5ab293b729 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1110,6 +1110,11 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
 
     // A8.6.3 ADC (register-shifted register)
     // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+    // 
+    // This also accounts for shift instructions (register) where, fortunately,
+    // Inst{19-16} = 0b0000.
+    // A8.6.89 LSL (register)
+    // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
     if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
         decodeRm(insn) == 15 || decodeRs(insn) == 15)
       return false;

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index e235d51896860b69678673e6034a652249f20a4d..a044b0d7db3c256672065f80dfb61ee79008bcf7 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -245,3 +245,6 @@
 
 # CHECK:       smlsldx r4, r12, r11, r4
 0x7b 0x44 0x4c 0xe7
+
+# CHECK:       lsl     r3, r2, r1
+0x12 0x31 0xa0 0xe1

diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
new file mode 100644 (file)
index 0000000..20293ad
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.89 LSL (register)
+# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+0x12 0xf1 0xa0 0xe1