AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10706

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240830 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.h b/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 0d40d14f8203e50ca669af292d0cd95c9a3810dd..27f269a95f9fb0135d3459409ed020b406765eb7 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -275,6 +275,13 @@ public:
   bool enableSubRegLiveness() const override {
     return true;
   }
   bool enableSubRegLiveness() const override {
     return true;
   }

+
+  /// \brief Returns the offset in bytes from the start of the input buffer
+  ///        of the first explicit kernel argument.
+  unsigned getExplicitKernelArgOffset() const {
+    return isAmdHsaOS() ? 0 : 36;
+  }
+

 };
 
 } // End namespace llvm
 };
 
 } // End namespace llvm

diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
index c73e4481a717e0398a148df977bd2b63a92efa4d..ead1a374347387c74ab9a8083a98f25583685093 100644 (file)
--- a/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -583,7 +583,8 @@ SDValue SITargetLowering::LowerFormalArguments(
     if (VA.isMemLoc()) {
       VT = Ins[i].VT;
       EVT MemVT = Splits[i].VT;
     if (VA.isMemLoc()) {
       VT = Ins[i].VT;
       EVT MemVT = Splits[i].VT;

-      const unsigned Offset = 36 + VA.getLocMemOffset();
+      const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
+                              VA.getLocMemOffset();

       // The first 36 bytes of the input buffer contains information about
       // thread group and global sizes.
       SDValue Arg = LowerParameter(DAG, VT, MemVT,  DL, DAG.getRoot(),
       // The first 36 bytes of the input buffer contains information about
       // thread group and global sizes.
       SDValue Arg = LowerParameter(DAG, VT, MemVT,  DL, DAG.getRoot(),

diff --git a/test/CodeGen/AMDGPU/hsa.ll b/test/CodeGen/AMDGPU/hsa.ll
index 3a76a36486109fb9f9ffcee1a114f39f7c85357f..3561d4a274dda3c0fc6622858f67d10fbe337198 100644 (file)
--- a/test/CodeGen/AMDGPU/hsa.ll
+++ b/test/CodeGen/AMDGPU/hsa.ll
@@ -5,6 +5,7 @@
 ; HSA-NEXT: .ascii  "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
 ; Test that the amd_kernel_code_t object is emitted
 ; HSA: .asciz
 ; HSA-NEXT: .ascii  "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
 ; Test that the amd_kernel_code_t object is emitted
 ; HSA: .asciz

+; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0

 ; Make sure we are setting the ATC bit:
 ; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
 ; Make sure we are setting the ATC bit:
 ; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0