Indexing off by one resulted in errant encoding of source register for

reg->reg moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57011 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 3936afc7171cadbaada2418534fe63b7954a64f1..a8fe2ea4f19f214a7e6a9d048f9a3564ccb9cad4 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -416,7 +416,7 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
   const MachineOperand &MO = MI.getOperand(OpIdx);
   if (MO.isReg())
     // Encode register Rm.
-    return Binary | getMachineOpValue(MI, NumDefs + 1);
+    return Binary | getMachineOpValue(MI, NumDefs);
 
   // Encode so_imm.
   // Set bit I(25) to identify this is the immediate form of <shifter_op>