static cl::opt<bool>
SplitEdges("machine-sink-split",
cl::desc("Split critical edges during machine sinking"),
- cl::init(false), cl::Hidden);
-static cl::opt<unsigned>
-SplitLimit("split-limit",
- cl::init(~0u), cl::Hidden);
+ cl::init(true), cl::Hidden);
STATISTIC(NumSunk, "Number of machine instructions sunk");
STATISTIC(NumSplit, "Number of critical edges split");
return 0;
// Avoid breaking back edge. From == To means backedge for single BB loop.
- if (!SplitEdges || NumSplit == SplitLimit || FromBB == ToBB)
+ if (!SplitEdges || FromBB == ToBB)
return 0;
// Check for backedges of more "complex" loops.
// BreakPHIEdge is true if all the uses are in the successor MBB being
// sunken into and they are all PHI nodes. In this case, machine-sink must
// break the critical edge first.
- if (NumSplit == SplitLimit)
- return false;
MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock,
SuccToSinkTo, BreakPHIEdge);
if (!NewSucc) {
volatile store i32 0, i32* %c, align 4
%0 = volatile load i32* %a, align 4 ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 3
+; CHECK: addiu $3, $zero, 0
%iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1]
%2 = volatile load i32* %c, align 4 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
-; CHECK: addu $4, $zero, $3
-; CHECK: addu $2, $5, $4
+; CHECK: addiu $3, $zero, 3
+; CHECK: addu $2, $5, $3
%iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1]
%4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1]
ret i32 %4
; CHECK: oeq_inff:
; CHECK: ucomiss
-; CHECK: jae
+; CHECK: jb
define float @oeq_inff(float %x, float %y) nounwind readonly {
%t0 = fcmp oeq float %x, 0x7FF0000000000000
%t1 = select i1 %t0, float 1.0, float %y
; CHECK: oeq_inf:
; CHECK: ucomisd
-; CHECK: jae
+; CHECK: jb
define double @oeq_inf(double %x, double %y) nounwind readonly {
%t0 = fcmp oeq double %x, 0x7FF0000000000000
%t1 = select i1 %t0, double 1.0, double %y
; CHECK: une_inff:
; CHECK: ucomiss
-; CHECK: jb
+; CHECK: jae
define float @une_inff(float %x, float %y) nounwind readonly {
%t0 = fcmp une float %x, 0x7FF0000000000000
%t1 = select i1 %t0, float 1.0, float %y
; CHECK: une_inf:
; CHECK: ucomisd
-; CHECK: jb
+; CHECK: jae
define double @une_inf(double %x, double %y) nounwind readonly {
%t0 = fcmp une double %x, 0x7FF0000000000000
%t1 = select i1 %t0, double 1.0, double %y
; CHECK: oeq_neg_inff:
; CHECK: ucomiss
-; CHECK: jae
+; CHECK: jb
define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
%t0 = fcmp oeq float %x, 0xFFF0000000000000
%t1 = select i1 %t0, float 1.0, float %y
; CHECK: oeq_neg_inf:
; CHECK: ucomisd
-; CHECK: jae
+; CHECK: jb
define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
%t0 = fcmp oeq double %x, 0xFFF0000000000000
%t1 = select i1 %t0, double 1.0, double %y
; CHECK: une_neg_inff:
; CHECK: ucomiss
-; CHECK: jb
+; CHECK: jae
define float @une_neg_inff(float %x, float %y) nounwind readonly {
%t0 = fcmp une float %x, 0xFFF0000000000000
%t1 = select i1 %t0, float 1.0, float %y
; CHECK: une_neg_inf:
; CHECK: ucomisd
-; CHECK: jb
+; CHECK: jae
define double @une_neg_inf(double %x, double %y) nounwind readonly {
%t0 = fcmp une double %x, 0xFFF0000000000000
%t1 = select i1 %t0, double 1.0, double %y
; that it's conditionally evaluated.
; CHECK: foo:
-; CHECK: divsd
; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: jne
+; CHECK-NEXT: je
; CHECK-NEXT: divsd
+; CHECK-NEXT: ret
+; CHECK: divsd
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
ret double %z
}
+; Make sure the critical edge is broken so the divsd is sunken below
+; the conditional branch.
+; rdar://8454886
+
+; CHECK: split:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: je
+; CHECK-NEXT: divsd
+; CHECK-NEXT: ret
+; CHECK: movaps
+; CHECK-NEXT: ret
+define double @split(double %x, double %y, i1 %c) nounwind {
+ %a = fdiv double %x, 3.2
+ %z = select i1 %c, double %a, double %y
+ ret double %z
+}
+
+
; Hoist floating-point constant-pool loads out of loops.
; CHECK: bar:
; Codegen should hoist and CSE these constants.
; CHECK: vv:
-; CHECK: LCPI2_0(%rip), %xmm0
-; CHECK: LCPI2_1(%rip), %xmm1
-; CHECK: LCPI2_2(%rip), %xmm2
+; CHECK: LCPI3_0(%rip), %xmm0
+; CHECK: LCPI3_1(%rip), %xmm1
+; CHECK: LCPI3_2(%rip), %xmm2
; CHECK: align
; CHECK-NOT: LCPI
; CHECK: ret
ret i32 %2
}
; CHECK: f3:
-; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
; CHECK-NEXT: ldc r0, 10
-; CHECK-NEXT: bt r1
; CHECK: ldc r0, 17
define i32 @f4(i32 %a) {
ret i32 %2
}
; CHECK: f4:
-; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
; CHECK-NEXT: ldc r0, 17
-; CHECK-NEXT: bt r1
; CHECK: ldc r0, 10
define i32 @f5(i32 %a) {