We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150
91177308-0d34-0410-b5e6-
96231b3b80d8
case TargetLowering::TypeLegal:
break;
case TargetLowering::TypePromoteInteger:
- if (NOutVT.bitsEq(NInVT))
+ if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
// The input promotes to the same size. Convert the promoted value.
return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
break;
--- /dev/null
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
+
+; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
+; CHECK: prom_bug
+; CHECK: movd
+; CHECK: shufb
+; CHECK: movw
+; CHECK: ret
+define void @prom_bug(<4 x i8> %t, i16* %p) {
+ %r = bitcast <4 x i8> %t to <2 x i16>
+ %o = extractelement <2 x i16> %r, i32 0
+ store i16 %o, i16* %p
+ ret void
+}
+
define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) {
entry:
+; CHECK: cfi_def_cfa_offset
; CHECK-NOT: set
; CHECK: pcmpgt
; CHECK: blendvps
; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
-; CHECK: incw
+; CHECK: incl
; CHECK: incl
; CHECK: incl
; CHECK: addl