Verify that explicit definitions in the TargetInstrDesc are matched by

explicit register define operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71933 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 25549b0269bf6c0091e799c0c117790e35093a59..4244b2178b8fc4752ffc7b8d87fcc999f726e716 100644 (file)
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -327,6 +327,18 @@ void
 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
 {
   const MachineInstr *MI = MO->getParent();
+  const TargetInstrDesc &TI = MI->getDesc();
+
+  // The first TI.NumDefs operands must be explicit register defines
+  if (MONum < TI.getNumDefs()) {
+    if (!MO->isReg())
+      report("Explicit definition must be a register", MO, MONum);
+    else if (!MO->isDef())
+      report("Explicit definition marked as use", MO, MONum);
+    else if (MO->isImplicit())
+      report("Explicit definition marked as implicit", MO, MONum);
+  }
+
   switch (MO->getType()) {
   case MachineOperand::MO_Register: {
     const unsigned Reg = MO->getReg();
@@ -374,7 +386,6 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
     }
 
     // Check register classes.
-    const TargetInstrDesc &TI = MI->getDesc();
     if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
       const TargetOperandInfo &TOI = TI.OpInfo[MONum];
       unsigned SubIdx = MO->getSubReg();