Fix emission of instructions that directly reference MBBs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7771 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/support/tools/TableGen/InstrSelectorEmitter.cpp b/support/tools/TableGen/InstrSelectorEmitter.cpp
index 9bc50cee7151346c19307cac12752b97f8539c35..28c7de1140372a04ba445056c42933c3c76dce40 100644 (file)
--- a/support/tools/TableGen/InstrSelectorEmitter.cpp
+++ b/support/tools/TableGen/InstrSelectorEmitter.cpp
@@ -1205,15 +1205,21 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
           if (P->getResult()) OS << ", NewReg";
           OS << ")";
 
-          for (unsigned i = 0, e = Operands.size(); i != e; ++i)
-            if (Operands[i].first->isLeaf()) {
-              Record *RV = Operands[i].first->getValueRecord();
+          for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+            TreePatternNode *Op = Operands[i].first;
+            if (Op->isLeaf()) {
+              Record *RV = Op->getValueRecord();
               assert(RV->isSubClassOf("RegisterClass") &&
                      "Only handles registers here so far!");
               OS << ".addReg(" << Operands[i].second << "->Val)";
-            } else {
+            } else if (Op->getOperator()->getName() == "imm") {
               OS << ".addZImm(" << Operands[i].second << "->Val)";
+            } else if (Op->getOperator()->getName() == "basicblock") {
+              OS << ".addMBB(" << Operands[i].second << "->Val)";
+            } else {
+              assert(0 && "Unknown value type!");
             }
+          }
           OS << ";\n";
           break;
         case Pattern::Expander: {

diff --git a/utils/TableGen/InstrSelectorEmitter.cpp b/utils/TableGen/InstrSelectorEmitter.cpp
index 9bc50cee7151346c19307cac12752b97f8539c35..28c7de1140372a04ba445056c42933c3c76dce40 100644 (file)
--- a/utils/TableGen/InstrSelectorEmitter.cpp
+++ b/utils/TableGen/InstrSelectorEmitter.cpp
@@ -1205,15 +1205,21 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
           if (P->getResult()) OS << ", NewReg";
           OS << ")";
 
-          for (unsigned i = 0, e = Operands.size(); i != e; ++i)
-            if (Operands[i].first->isLeaf()) {
-              Record *RV = Operands[i].first->getValueRecord();
+          for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+            TreePatternNode *Op = Operands[i].first;
+            if (Op->isLeaf()) {
+              Record *RV = Op->getValueRecord();
               assert(RV->isSubClassOf("RegisterClass") &&
                      "Only handles registers here so far!");
               OS << ".addReg(" << Operands[i].second << "->Val)";
-            } else {
+            } else if (Op->getOperator()->getName() == "imm") {
               OS << ".addZImm(" << Operands[i].second << "->Val)";
+            } else if (Op->getOperator()->getName() == "basicblock") {
+              OS << ".addMBB(" << Operands[i].second << "->Val)";
+            } else {
+              assert(0 && "Unknown value type!");
             }
+          }
           OS << ";\n";
           break;
         case Pattern::Expander: {