set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils)
-set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport)
#include "MBlaze.h"
#include "MBlazeSubtarget.h"
+#include "MBlazeRegisterInfo.h"
#include "MBlazeISelLowering.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
MBlazeOperand *ParseFsl();
MBlazeOperand* ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+ bool ParseDirectiveWord(unsigned Size, SMLoc L);
+
bool MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out);
void addMemOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::CreateReg(getMemBase()));
+
unsigned RegOff = getMemOffReg();
if (RegOff)
Inst.addOperand(MCOperand::CreateReg(RegOff));
else
addExpr(Inst, getMemOff());
-
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
}
StringRef getToken() const {
getImm()->print(OS);
break;
case Register:
- OS << "<register " << getReg() << ">";
+ OS << "<register R";
+ OS << MBlazeRegisterInfo::getRegisterNumbering(getReg()) << ">";
break;
case Token:
OS << "'" << getToken() << "'";
break;
- case Memory:
- OS << "MEMORY";
+ case Memory: {
+ OS << "<memory R";
+ OS << MBlazeRegisterInfo::getRegisterNumbering(getMemBase());
+ OS << ", ";
+
+ unsigned RegOff = getMemOffReg();
+ if (RegOff)
+ OS << "R" << MBlazeRegisterInfo::getRegisterNumbering(RegOff);
+ else
+ OS << getMemOff();
+ OS << ">";
+ }
break;
case Fsl:
getFslImm()->print(OS);
if (RegNo == 0)
return 0;
+ getLexer().Lex();
return MBlazeOperand::CreateReg(RegNo, S, E);
}
}
if (reg >= 16)
return 0;
+ getLexer().Lex();
const MCExpr *EVal = MCConstantExpr::Create(reg,getContext());
return MBlazeOperand::CreateFslImm(EVal,S,E);
}
return 0;
}
- // Move past the parsed token in the token stream
- getLexer().Lex();
-
// Push the parsed operand into the list of operands
Operands.push_back(Op);
return Op;
bool MBlazeAsmParser::
ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
- // The first operand is the token for the instruction name
- Operands.push_back(MBlazeOperand::CreateToken(Name, NameLoc));
+ // The first operands is the token for the instruction name
+ size_t dotLoc = Name.find('.');
+ Operands.push_back(MBlazeOperand::CreateToken(Name.substr(0,dotLoc),NameLoc));
+ if (dotLoc < Name.size())
+ Operands.push_back(MBlazeOperand::CreateToken(Name.substr(dotLoc),NameLoc));
// If there are no more operands then finish
if (getLexer().is(AsmToken::EndOfStatement))
while (getLexer().isNot(AsmToken::EndOfStatement) &&
getLexer().is(AsmToken::Comma)) {
- // Make sure there is a comma separating operands
- // if (getLexer().isNot(AsmToken::Comma))
- // return false;
-
// Consume the comma token
getLexer().Lex();
if (Name.startswith("lw") || Name.startswith("sw") ||
Name.startswith("lh") || Name.startswith("sh") ||
Name.startswith("lb") || Name.startswith("sb"))
- return ParseMemory(Operands);
+ return (ParseMemory(Operands) == NULL);
return false;
}
/// ParseDirective parses the arm specific directives
bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) {
+ StringRef IDVal = DirectiveID.getIdentifier();
+ if (IDVal == ".word")
+ return ParseDirectiveWord(2, DirectiveID.getLoc());
return true;
}
+/// ParseDirectiveWord
+/// ::= .word [ expression (, expression)* ]
+bool MBlazeAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ for (;;) {
+ const MCExpr *Value;
+ if (getParser().ParseExpression(Value))
+ return true;
+
+ getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
+
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ // FIXME: Improve diagnostic.
+ if (getLexer().isNot(AsmToken::Comma))
+ return Error(L, "unexpected token in directive");
+ Parser.Lex();
+ }
+ }
+
+ Parser.Lex();
+ return false;
+}
+
extern "C" void LLVMInitializeMBlazeAsmLexer();
/// Force static initialization.
printInstruction(MI, O);
}
-void MBlazeInstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- if (Op.isImm())
- O << Op.getImm();
- else {
- assert(Op.isExpr() && "unknown pcrel immediate operand");
- O << *Op.getExpr();
- }
-}
-
void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier) {
assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
}
}
-void MBlazeInstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O,
- const char *Modifier) {
- const MCOperand &Base = MI->getOperand(OpNo);
- const MCOperand &Disp = MI->getOperand(OpNo+1);
-
- // Print displacement first
-
- // If the global address expression is a part of displacement field with a
- // register base, we should not emit any prefix symbol here, e.g.
- // mov.w &foo, r1
- // vs
- // mov.w glb(r1), r2
- // Otherwise (!) msp430-as will silently miscompile the output :(
- if (!Base.getReg())
- O << '&';
-
- if (Disp.isExpr())
- O << *Disp.getExpr();
- else {
- assert(Disp.isImm() && "Expected immediate in displacement field");
- O << Disp.getImm();
- }
-
- // Print register base field
- if (Base.getReg())
- O << getRegisterName(Base.getReg());
-}
-
void MBlazeInstPrinter::printFSLImm(const MCInst *MI, int OpNo,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNo);
void MBlazeInstPrinter::printMemOperand(const MCInst *MI, int OpNo,
raw_ostream &O, const char *Modifier) {
- printOperand(MI, OpNo+1, O, NULL);
- O << ", ";
printOperand(MI, OpNo, O, NULL);
+ O << ", ";
+ printOperand(MI, OpNo+1, O, NULL);
}
-
-/*
-void MBlazeInstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned CC = MI->getOperand(OpNo).getImm();
-
- switch (CC) {
- default:
- llvm_unreachable("Unsupported CC code");
- break;
- case MBlazeCC::COND_E:
- O << "eq";
- break;
- case MBlazeCC::COND_NE:
- O << "ne";
- break;
- case MBlazeCC::COND_HS:
- O << "hs";
- break;
- case MBlazeCC::COND_LO:
- O << "lo";
- break;
- case MBlazeCC::COND_GE:
- O << "ge";
- break;
- case MBlazeCC::COND_L:
- O << 'l';
- break;
- }
-}
-*/
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = 0);
- void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
- const char *Modifier = 0);
void printFSLImm(const MCInst *MI, int OpNo, raw_ostream &O);
void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O);
void printMemOperand(const MCInst *MI, int OpNo,raw_ostream &O,
void MBlazeAsmPrinter::
printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier) {
- printOperand(MI, opNum+1, O);
- O << ", ";
printOperand(MI, opNum, O);
+ O << ", ";
+ printOperand(MI, opNum+1, O);
}
static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T,
N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
return false; // jump tables.
- Base = N.getOperand(1);
- Index = N.getOperand(0);
+ Base = N.getOperand(0);
+ Index = N.getOperand(1);
return true;
}
/// a signed 32-bit displacement [r+imm], and if it is not better
/// represented as reg+reg.
bool MBlazeDAGToDAGISel::
-SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base) {
+SelectAddrRegImm(SDValue N, SDValue &Base, SDValue &Disp) {
// If this can be more profitably realized as r+r, fail.
- if (SelectAddrRegReg(N, Disp, Base))
+ if (SelectAddrRegReg(N, Base, Disp))
return false;
if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> :
- TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
- !strconcat(instr_asm, " $dst, $c, $b"),
- [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
+ TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
+ !strconcat(instr_asm, " $dst, $c, $b"),
+ [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
class LogicF<bits<6> op, string instr_asm> :
TB<op, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
+}
+let Predicates=[HasFPU], isCodeGenOnly=1 in {
def LWF : LoadFM<0x32, "lw ", load>;
- def LWFI : LoadFMI<0x32, "lwi ", load>;
+ def LWFI : LoadFMI<0x3A, "lwi ", load>;
- def SWF : StoreFM<0x32, "sw ", store>;
- def SWFI : StoreFMI<0x32, "swi ", store>;
+ def SWF : StoreFM<0x36, "sw ", store>;
+ def SWFI : StoreFMI<0x3E, "swi ", store>;
}
let Predicates=[HasFPU,HasSqrt] in {
def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
- def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>;
+ def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIAlu>;
}
let isAsCheapAsAMove = 1 in {
}
def FPseudo : Format<0>;
-def FRRR : Format<1>; // ADD, RSUB, OR, etc.
-def FRRI : Format<2>; // ADDI, RSUBI, ORI, etc.
+def FRRR : Format<1>; // ADD, OR, etc.
+def FRRI : Format<2>; // ADDI, ORI, etc.
def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
def FRCR : Format<5>; // BRLD, BRALD, GETD
def FCX : Format<15>; // TPUT
def FCR : Format<16>; // TPUTD
def FRIR : Format<17>; // RSUBI
-def FC : Format<18>; // NOP
+def FRRRR : Format<18>; // RSUB, FRSUB
+def FRI : Format<19>; // RSUB, FRSUB
+def FC : Format<20>; // NOP
//===----------------------------------------------------------------------===//
// Describe MBlaze instructions format
//===----------------------------------------------------------------------===//
// Generic MBlaze Format
-class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
+class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin> : Instruction {
let Namespace = "MBlaze";
field bits<32> Inst;
// If the instruction is marked as a pseudo, set isCodeGenOnly so that the
// assembler and disassmbler ignore it.
let isCodeGenOnly = !eq(!cast<string>(form), "FPseudo");
-
+
dag OutOperandList = outs;
dag InOperandList = ins;
let Inst{16-31} = imm16;
}
+//===----------------------------------------------------------------------===//
+// Type A instruction class in MBlaze but with the operands reversed
+// in the LLVM DAG : <|opcode|rd|ra|rb|flags|>
+//===----------------------------------------------------------------------===//
+
+class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
+ list<dag> pattern, InstrItinClass itin> :
+ MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
+{
+ bits<5> rd;
+ bits<5> rb;
+ bits<5> ra;
+
+ let Form = FRRRR;
+
+ let Inst{6-10} = rd;
+ let Inst{11-15} = ra;
+ let Inst{16-20} = rb;
+ let Inst{21-31} = flags;
+}
+
//===----------------------------------------------------------------------===//
// Type B instruction class in MBlaze but with the operands reversed in
// the LLVM DAG : <|opcode|rd|ra|immediate|>
let ra = rra;
let imm16 = rimm16;
}
+
+//===----------------------------------------------------------------------===//
+// Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|>
+//===----------------------------------------------------------------------===//
+class SHT<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
+ list<dag> pattern, InstrItinClass itin> :
+ MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin> {
+ bits<5> rd;
+ bits<5> ra;
+ bits<5> imm5;
+
+ let Inst{6-10} = rd;
+ let Inst{11-15} = ra;
+ let Inst{16-20} = 0x0;
+ let Inst{21-22} = flags;
+ let Inst{23-26} = 0x0;
+ let Inst{27-31} = imm5;
+}
+
+//===----------------------------------------------------------------------===//
+// Special instruction class in MBlaze : <|opcode|rd|imm14|>
+//===----------------------------------------------------------------------===//
+class SPC<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
+ list<dag> pattern, InstrItinClass itin> :
+ MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
+ bits<5> rd;
+ bits<14> imm14;
+
+ let Inst{6-10} = rd;
+ let Inst{11-15} = 0x0;
+ let Inst{16-17} = flags;
+ let Inst{18-31} = imm14;
+}
+
+//===----------------------------------------------------------------------===//
+// MSR instruction class in MBlaze : <|opcode|rd|imm15|>
+//===----------------------------------------------------------------------===//
+class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
+ list<dag> pattern, InstrItinClass itin> :
+ MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
+ bits<5> rd;
+ bits<15> imm15;
+
+ let Inst{6-10} = rd;
+ let Inst{11-16} = flags;
+ let Inst{17-31} = imm15;
+}
unsigned MBlazeInstrInfo::
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
if (MI->getOpcode() == MBlaze::LWI) {
- if ((MI->getOperand(2).isFI()) && // is a stack slot
- (MI->getOperand(1).isImm()) && // the imm is zero
- (isZeroImm(MI->getOperand(1)))) {
- FrameIndex = MI->getOperand(2).getIndex();
+ if ((MI->getOperand(1).isFI()) && // is a stack slot
+ (MI->getOperand(2).isImm()) && // the imm is zero
+ (isZeroImm(MI->getOperand(2)))) {
+ FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
unsigned MBlazeInstrInfo::
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
if (MI->getOpcode() == MBlaze::SWI) {
- if ((MI->getOperand(2).isFI()) && // is a stack slot
- (MI->getOperand(1).isImm()) && // the imm is zero
- (isZeroImm(MI->getOperand(1)))) {
- FrameIndex = MI->getOperand(2).getIndex();
+ if ((MI->getOperand(1).isFI()) && // is a stack slot
+ (MI->getOperand(2).isImm()) && // the imm is zero
+ (isZeroImm(MI->getOperand(2)))) {
+ FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
}
void MBlazeInstrInfo::
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
}
//===----------------------------------------------------------------------===//
FCX,
FCR,
FRIR,
+ FRRRR,
+ FRI,
FC,
FormMask = 63
def calltarget : Operand<i32>;
def simm16 : Operand<i32>;
def uimm5 : Operand<i32>;
+def uimm14 : Operand<i32>;
+def uimm15 : Operand<i32>;
def fimm : Operand<f32>;
// Unsigned Operand
// Address operand
def memri : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops simm16, GPR);
+ let MIOperandInfo = (ops GPR, simm16);
let ParserMatchClass = MBlazeMemAsmOperand;
}
!strconcat(instr_asm, " $dst, $b, $c"),
[(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
+class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
+ Operand Od, PatLeaf imm_type> :
+ SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
+ !strconcat(instr_asm, " $dst, $b, $c"),
+ [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>;
+
class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> :
- TA<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
+ TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
!strconcat(instr_asm, " $dst, $c, $b"),
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> :
- TA<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
- !strconcat(instr_asm, " $dst, $b, $c"),
- [], itin>;
+ TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
+ !strconcat(instr_asm, " $dst, $b, $c"),
+ [], itin>;
class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
- TB<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
- !strconcat(instr_asm, " $dst, $b, $c"),
- [], IIAlu>;
+ TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
+ !strconcat(instr_asm, " $dst, $b, $c"),
+ [], IIAlu>;
//===----------------------------------------------------------------------===//
// Misc Arithmetic Instructions
//===----------------------------------------------------------------------===//
// Memory Access Instructions
//===----------------------------------------------------------------------===//
-class LoadM<bits<6> op, string instr_asm, PatFrag OpNode> :
- TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
- !strconcat(instr_asm, " $dst, $addr"),
- [(set (i32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
-
-class LoadW<bits<6> op, bits<11> flags, string instr_asm> :
+class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"),
[], IILoad>;
class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
- TBR<op, (outs GPR:$dst), (ins memri:$addr),
- !strconcat(instr_asm, " $dst, $addr"),
- [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
-
-class StoreM<bits<6> op, string instr_asm, PatFrag OpNode> :
- TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
+ TB<op, (outs GPR:$dst), (ins memri:$addr),
!strconcat(instr_asm, " $dst, $addr"),
- [(OpNode (i32 GPR:$dst), xaddr:$addr)], IIStore>;
+ [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
-class StoreW<bits<6> op, bits<11> flags, string instr_asm> :
+class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"),
[], IIStore>;
class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
- TBR<op, (outs), (ins GPR:$dst, memri:$addr),
- !strconcat(instr_asm, " $dst, $addr"),
- [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>;
+ TB<op, (outs), (ins GPR:$dst, memri:$addr),
+ !strconcat(instr_asm, " $dst, $addr"),
+ [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>;
//===----------------------------------------------------------------------===//
// Branch Instructions
def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>;
def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>;
def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>;
- def BSRLI : ArithI<0x11, "bsrli ", srl, uimm5, immZExt5>;
- def BSRAI : ArithI<0x11, "bsrai ", sra, uimm5, immZExt5>;
- def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>;
+ def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>;
+ def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>;
+ def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>;
}
let Predicates=[HasDiv] in {
//===----------------------------------------------------------------------===//
let canFoldAsLoad = 1, isReMaterializable = 1 in {
- def LBU : LoadM<0x30, "lbu ", zextloadi8>;
- def LHU : LoadM<0x31, "lhu ", zextloadi16>;
+ def LBU : LoadM<0x30, 0x000, "lbu ">;
+ def LBUR : LoadM<0x30, 0x200, "lbur ">;
+
+ def LHU : LoadM<0x31, 0x000, "lhu ">;
+ def LHUR : LoadM<0x31, 0x200, "lhur ">;
- def LW : LoadW<0x32, 0x0, "lw ">;
- def LWR : LoadW<0x32, 0x2, "lwr ">;
- def LWX : LoadW<0x32, 0x4, "lwx ">;
+ def LW : LoadM<0x32, 0x000, "lw ">;
+ def LWR : LoadM<0x32, 0x200, "lwr ">;
+ def LWX : LoadM<0x32, 0x400, "lwx ">;
def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
def LWI : LoadMI<0x3A, "lwi ", load>;
}
- def SB : StoreM<0x34, "sb ", truncstorei8>;
- def SH : StoreM<0x35, "sh ", truncstorei16>;
+ def SB : StoreM<0x34, 0x000, "sb ">;
+ def SBR : StoreM<0x34, 0x200, "sbr ">;
- def SW : StoreW<0x36, 0x0, "sw ">;
- def SWR : StoreW<0x36, 0x2, "swr ">;
- def SWX : StoreW<0x36, 0x4, "swx ">;
+ def SH : StoreM<0x35, 0x000, "sh ">;
+ def SHR : StoreM<0x35, 0x200, "shr ">;
+
+ def SW : StoreM<0x36, 0x000, "sw ">;
+ def SWR : StoreM<0x36, 0x200, "swr ">;
+ def SWX : StoreM<0x36, 0x400, "swx ">;
def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
//===----------------------------------------------------------------------===//
// Misc. instructions
//===----------------------------------------------------------------------===//
-def MFS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mfs", [], IIAlu> {
-}
+def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg),
+ "mfs $dst, $rg", [], IIAlu>;
-def MTS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mts", [], IIAlu> {
-}
+def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg),
+ "mts $dst, $rg", [], IIAlu>;
-def MSRSET : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrset", [], IIAlu> {
-}
+def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
+ "msrset $dst, $set", [], IIAlu>;
-def MSRCLR : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrclr", [], IIAlu> {
-}
+def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr),
+ "msrclr $dst, $clr", [], IIAlu>;
let rd=0x0, Form=FCRR in {
def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
+// 16-bit load and store
+def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>;
+def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>;
+
+// 8-bit load and store
+def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>;
+def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>;
+
// Peepholes
def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
//===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===//
-//
+//DJ
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// swi R15, R1, stack_loc
if (MFI->adjustsStack()) {
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
- .addReg(MBlaze::R15).addImm(RAOffset).addReg(MBlaze::R1);
+ .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset);
}
// if framepointer enabled, save it and set it
if (hasFP(MF)) {
// swi R19, R1, stack_loc
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
- .addReg(MBlaze::R19).addImm(FPOffset).addReg(MBlaze::R1);
+ .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset);
// add R19, R1, R0
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
// lwi R19, R1, stack_loc
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19)
- .addImm(FPOffset).addReg(MBlaze::R1);
+ .addReg(MBlaze::R1).addImm(FPOffset);
}
// Restore the return address only if the function isnt a leaf one.
// lwi R15, R1, stack_loc
if (MFI->adjustsStack()) {
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15)
- .addImm(RAOffset).addReg(MBlaze::R1);
+ .addReg(MBlaze::R1).addImm(RAOffset);
}
// Get the number of bytes from FrameInfo
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to make sure that all of the TYPE-A instructions supported by
+# the Microblaze can be parsed by the assembly parser.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 000000 00000 00000 00000 00000000000
+
+# CHECK: beq
+# BINARY: 100111 00000 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0x02,0x18,0x00]
+ beq r2, r3
+
+# CHECK: bge
+# BINARY: 100111 00101 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0xa2,0x18,0x00]
+ bge r2, r3
+
+# CHECK: bgt
+# BINARY: 100111 00100 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0x82,0x18,0x00]
+ bgt r2, r3
+
+# CHECK: ble
+# BINARY: 100111 00011 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0x62,0x18,0x00]
+ ble r2, r3
+
+# CHECK: blt
+# BINARY: 100111 00010 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0x42,0x18,0x00]
+ blt r2, r3
+
+# CHECK: bne
+# BINARY: 100111 00001 00010 00011 00000000000
+# CHECK: encoding: [0x9c,0x22,0x18,0x00]
+ bne r2, r3
+
+# CHECK: beqd
+# BINARY: 100111 10000 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0x02,0x18,0x00]
+ beqd r2, r3
+
+# CHECK: bged
+# BINARY: 100111 10101 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0xa2,0x18,0x00]
+ bged r2, r3
+
+# CHECK: bgtd
+# BINARY: 100111 10100 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0x82,0x18,0x00]
+ bgtd r2, r3
+
+# CHECK: bled
+# BINARY: 100111 10011 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0x62,0x18,0x00]
+ bled r2, r3
+
+# CHECK: bltd
+# BINARY: 100111 10010 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0x42,0x18,0x00]
+ bltd r2, r3
+
+# CHECK: bned
+# BINARY: 100111 10001 00010 00011 00000000000
+# CHECK: encoding: [0x9e,0x22,0x18,0x00]
+ bned r2, r3
+
+# CHECK: br
+# BINARY: 100110 00000 00000 00011 00000000000
+# CHECK: encoding: [0x98,0x00,0x18,0x00]
+ br r3
+
+# CHECK: bra
+# BINARY: 100110 00000 01000 00011 00000000000
+# CHECK: encoding: [0x98,0x08,0x18,0x00]
+ bra r3
+
+# CHECK: brd
+# BINARY: 100110 00000 10000 00011 00000000000
+# CHECK: encoding: [0x98,0x10,0x18,0x00]
+ brd r3
+
+# CHECK: brad
+# BINARY: 100110 00000 11000 00011 00000000000
+# CHECK: encoding: [0x98,0x18,0x18,0x00]
+ brad r3
+
+# CHECK: brld
+# BINARY: 100110 01111 10100 00011 00000000000
+# CHECK: encoding: [0x99,0xf4,0x18,0x00]
+ brld r15, r3
+
+# CHECK: brald
+# BINARY: 100110 01111 11100 00011 00000000000
+# CHECK: encoding: [0x99,0xfc,0x18,0x00]
+ brald r15, r3
+
+# CHECK: brk
+# BINARY: 100110 01111 01100 00011 00000000000
+# CHECK: encoding: [0x99,0xec,0x18,0x00]
+ brk r15, r3
+
+# CHECK: beqi
+# BINARY: 101111 00000 00010 0000000000000000
+# CHECK: encoding: [0xbc,0x02,0x00,0x00]
+ beqi r2, 0
+
+# CHECK: bgei
+# BINARY: 101111 00101 00010 0000000000000000
+# CHECK: encoding: [0xbc,0xa2,0x00,0x00]
+ bgei r2, 0
+
+# CHECK: bgti
+# BINARY: 101111 00100 00010 0000000000000000
+# CHECK: encoding: [0xbc,0x82,0x00,0x00]
+ bgti r2, 0
+
+# CHECK: blei
+# BINARY: 101111 00011 00010 0000000000000000
+# CHECK: encoding: [0xbc,0x62,0x00,0x00]
+ blei r2, 0
+
+# CHECK: blti
+# BINARY: 101111 00010 00010 0000000000000000
+# CHECK: encoding: [0xbc,0x42,0x00,0x00]
+ blti r2, 0
+
+# CHECK: bnei
+# BINARY: 101111 00001 00010 0000000000000000
+# CHECK: encoding: [0xbc,0x22,0x00,0x00]
+ bnei r2, 0
+
+# CHECK: beqid
+# BINARY: 101111 10000 00010 0000000000000000
+# CHECK: encoding: [0xbe,0x02,0x00,0x00]
+ beqid r2, 0
+
+# CHECK: bgeid
+# BINARY: 101111 10101 00010 0000000000000000
+# CHECK: encoding: [0xbe,0xa2,0x00,0x00]
+ bgeid r2, 0
+
+# CHECK: bgtid
+# BINARY: 101111 10100 00010 0000000000000000
+# CHECK: encoding: [0xbe,0x82,0x00,0x00]
+ bgtid r2, 0
+
+# CHECK: bleid
+# BINARY: 101111 10011 00010 0000000000000000
+# CHECK: encoding: [0xbe,0x62,0x00,0x00]
+ bleid r2, 0
+
+# CHECK: bltid
+# BINARY: 101111 10010 00010 0000000000000000
+# CHECK: encoding: [0xbe,0x42,0x00,0x00]
+ bltid r2, 0
+
+# CHECK: bneid
+# BINARY: 101111 10001 00010 0000000000000000
+# CHECK: encoding: [0xbe,0x22,0x00,0x00]
+ bneid r2, 0
+
+# CHECK: bri
+# BINARY: 101110 00000 00000 0000000000000000
+# CHECK: encoding: [0xb8,0x00,0x00,0x00]
+ bri 0
+
+# CHECK: brai
+# BINARY: 101110 00000 01000 0000000000000000
+# CHECK: encoding: [0xb8,0x08,0x00,0x00]
+ brai 0
+
+# CHECK: brid
+# BINARY: 101110 00000 10000 0000000000000000
+# CHECK: encoding: [0xb8,0x10,0x00,0x00]
+ brid 0
+
+# CHECK: braid
+# BINARY: 101110 00000 11000 0000000000000000
+# CHECK: encoding: [0xb8,0x18,0x00,0x00]
+ braid 0
+
+# CHECK: brlid
+# BINARY: 101110 01111 10100 0000000000000000
+# CHECK: encoding: [0xb9,0xf4,0x00,0x00]
+ brlid r15, 0
+
+# CHECK: bralid
+# BINARY: 101110 01111 11100 0000000000000000
+# CHECK: encoding: [0xb9,0xfc,0x00,0x00]
+ bralid r15, 0
+
+# CHECK: brki
+# BINARY: 101110 01111 01100 0000000000000000
+# CHECK: encoding: [0xb9,0xec,0x00,0x00]
+ brki r15, 0
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to ensure that all FPU instructions can be parsed by the
+# assembly parser correctly.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 011011 00000 00000 00000 00000000000
+
+# CHECK: fadd
+# BINARY: 010110 00000 00001 00010 00000000000
+# CHECK: encoding: [0x58,0x01,0x10,0x00]
+ fadd r0, r1, r2
+
+# CHECK: frsub
+# BINARY: 010110 00000 00001 00010 00010000000
+# CHECK: encoding: [0x58,0x01,0x10,0x80]
+ frsub r0, r1, r2
+
+# CHECK: fmul
+# BINARY: 010110 00000 00001 00010 00100000000
+# CHECK: encoding: [0x58,0x01,0x11,0x00]
+ fmul r0, r1, r2
+
+# CHECK: fdiv
+# BINARY: 010110 00000 00001 00010 00110000000
+# CHECK: encoding: [0x58,0x01,0x11,0x80]
+ fdiv r0, r1, r2
+
+# CHECK: fsqrt
+# BINARY: 010110 00000 00001 00000 01110000000
+# CHECK: encoding: [0x58,0x01,0x03,0x80]
+ fsqrt r0, r1
+
+# CHECK: fint
+# BINARY: 010110 00000 00001 00000 01100000000
+# CHECK: encoding: [0x58,0x01,0x03,0x00]
+ fint r0, r1
+
+# CHECK: flt
+# BINARY: 010110 00000 00001 00000 01010000000
+# CHECK: encoding: [0x58,0x01,0x02,0x80]
+ flt r0, r1
+
+# CHECK: fcmp.un
+# BINARY: 010110 00000 00001 00010 01000000000
+# CHECK: encoding: [0x58,0x01,0x12,0x00]
+ fcmp.un r0, r1, r2
+
+# CHECK: fcmp.lt
+# BINARY: 010110 00000 00001 00010 01000010000
+# CHECK: encoding: [0x58,0x01,0x12,0x10]
+ fcmp.lt r0, r1, r2
+
+# CHECK: fcmp.eq
+# BINARY: 010110 00000 00001 00010 01000100000
+# CHECK: encoding: [0x58,0x01,0x12,0x20]
+ fcmp.eq r0, r1, r2
+
+# CHECK: fcmp.le
+# BINARY: 010110 00000 00001 00010 01000110000
+# CHECK: encoding: [0x58,0x01,0x12,0x30]
+ fcmp.le r0, r1, r2
+
+# CHECK: fcmp.gt
+# BINARY: 010110 00000 00001 00010 01001000000
+# CHECK: encoding: [0x58,0x01,0x12,0x40]
+ fcmp.gt r0, r1, r2
+
+# CHECK: fcmp.ne
+# BINARY: 010110 00000 00001 00010 01001010000
+# CHECK: encoding: [0x58,0x01,0x12,0x50]
+ fcmp.ne r0, r1, r2
+
+# CHECK: fcmp.ge
+# BINARY: 010110 00000 00001 00010 01001100000
+# CHECK: encoding: [0x58,0x01,0x12,0x60]
+ fcmp.ge r0, r1, r2
# TYPE FD: OPCODE RD RB NCTAE
# BINARY: 011011 00000 00000 00000 0 00000 00000
+# TYPE FP: OPCODE RA NCTA FSL
+# 000000 00000 00000 1 0000 0000000 0000
+
# CHECK: get
# BINARY: 011011 00000 000000 00000 000000 0000
# CHECK: encoding: [0x6c,0x00,0x00,0x00]
# CHECK: encoding: [0x6c,0x00,0x7c,0x00]
tnecaget r0, rfsl0
+# CHECK: getd
+# BINARY: 010011 00000 00000 00001 0 00000 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0x00]
+ getd r0, r1
+
+# CHECK: ngetd
+# BINARY: 010011 00000 00000 00001 0 10000 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0x00]
+ ngetd r0, r1
+
+# CHECK: cgetd
+# BINARY: 010011 00000 00000 00001 0 01000 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0x00]
+ cgetd r0, r1
+
+# CHECK: ncgetd
+# BINARY: 010011 00000 00000 00001 0 11000 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0x00]
+ ncgetd r0, r1
+
+# CHECK: tgetd
+# BINARY: 010011 00000 00000 00001 0 00100 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0x80]
+ tgetd r0, r1
+
+# CHECK: tngetd
+# BINARY: 010011 00000 00000 00001 0 10100 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0x80]
+ tngetd r0, r1
+
+# CHECK: tcgetd
+# BINARY: 010011 00000 00000 00001 0 01100 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0x80]
+ tcgetd r0, r1
+
+# CHECK: tncgetd
+# BINARY: 010011 00000 00000 00001 0 11100 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0x80]
+ tncgetd r0, r1
+
+# CHECK: agetd
+# BINARY: 010011 00000 00000 00001 0 00010 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0x40]
+ agetd r0, r1
+
+# CHECK: nagetd
+# BINARY: 010011 00000 00000 00001 0 10010 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0x40]
+ nagetd r0, r1
+
+# CHECK: cagetd
+# BINARY: 010011 00000 00000 00001 0 01010 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0x40]
+ cagetd r0, r1
+
+# CHECK: ncagetd
+# BINARY: 010011 00000 00000 00001 0 11010 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0x40]
+ ncagetd r0, r1
+
+# CHECK: tagetd
+# BINARY: 010011 00000 00000 00001 0 00110 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0xc0]
+ tagetd r0, r1
+
+# CHECK: tnagetd
+# BINARY: 010011 00000 00000 00001 0 10110 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0xc0]
+ tnagetd r0, r1
+
+# CHECK: tcagetd
+# BINARY: 010011 00000 00000 00001 0 01110 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0xc0]
+ tcagetd r0, r1
+
+# CHECK: tncagetd
+# BINARY: 010011 00000 00000 00001 0 11110 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0xc0]
+ tncagetd r0, r1
+
+# CHECK: egetd
+# BINARY: 010011 00000 00000 00001 0 00001 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0x20]
+ egetd r0, r1
+
+# CHECK: negetd
+# BINARY: 010011 00000 00000 00001 0 10001 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0x20]
+ negetd r0, r1
+
+# CHECK: ecgetd
+# BINARY: 010011 00000 00000 00001 0 01001 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0x20]
+ ecgetd r0, r1
+
+# CHECK: necgetd
+# BINARY: 010011 00000 00000 00001 0 11001 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0x20]
+ necgetd r0, r1
+
+# CHECK: tegetd
+# BINARY: 010011 00000 00000 00001 0 00101 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0xa0]
+ tegetd r0, r1
+
+# CHECK: tnegetd
+# BINARY: 010011 00000 00000 00001 0 10101 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0xa0]
+ tnegetd r0, r1
+
+# CHECK: tecgetd
+# BINARY: 010011 00000 00000 00001 0 01101 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0xa0]
+ tecgetd r0, r1
+
+# CHECK: tnecgetd
+# BINARY: 010011 00000 00000 00001 0 11101 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0xa0]
+ tnecgetd r0, r1
+
+# CHECK: eagetd
+# BINARY: 010011 00000 00000 00001 0 00011 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0x60]
+ eagetd r0, r1
+
+# CHECK: neagetd
+# BINARY: 010011 00000 00000 00001 0 10011 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0x60]
+ neagetd r0, r1
+
+# CHECK: ecagetd
+# BINARY: 010011 00000 00000 00001 0 01011 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0x60]
+ ecagetd r0, r1
+
+# CHECK: necagetd
+# BINARY: 010011 00000 00000 00001 0 11011 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0x60]
+ necagetd r0, r1
+
+# CHECK: teagetd
+# BINARY: 010011 00000 00000 00001 0 00111 00000
+# CHECK: encoding: [0x4c,0x00,0x08,0xe0]
+ teagetd r0, r1
+
+# CHECK: tneagetd
+# BINARY: 010011 00000 00000 00001 0 10111 00000
+# CHECK: encoding: [0x4c,0x00,0x0a,0xe0]
+ tneagetd r0, r1
+
+# CHECK: tecagetd
+# BINARY: 010011 00000 00000 00001 0 01111 00000
+# CHECK: encoding: [0x4c,0x00,0x09,0xe0]
+ tecagetd r0, r1
+
+# CHECK: tnecagetd
+# BINARY: 010011 00000 00000 00001 0 11111 00000
+# CHECK: encoding: [0x4c,0x00,0x0b,0xe0]
+ tnecagetd r0, r1
+
+# CHECK: put
+# BINARY: 011011 00000 00000 1 0000 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0x80,0x00]
+ put r0, rfsl0
+
+# CHECK: aput
+# BINARY: 011011 00000 00000 1 0001 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0x88,0x00]
+ aput r0, rfsl0
+
+# CHECK: cput
+# BINARY: 011011 00000 00000 1 0100 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xa0,0x00]
+ cput r0, rfsl0
+
+# CHECK: caput
+# BINARY: 011011 00000 00000 1 0101 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xa8,0x00]
+ caput r0, rfsl0
+
+# CHECK: nput
+# BINARY: 011011 00000 00000 1 1000 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xc0,0x00]
+ nput r0, rfsl0
+
+# CHECK: naput
+# BINARY: 011011 00000 00000 1 1001 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xc8,0x00]
+ naput r0, rfsl0
+
+# CHECK: ncput
+# BINARY: 011011 00000 00000 1 1100 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xe0,0x00]
+ ncput r0, rfsl0
+
+# CHECK: ncaput
+# BINARY: 011011 00000 00000 1 1101 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xe8,0x00]
+ ncaput r0, rfsl0
+
+# CHECK: tput
+# BINARY: 011011 00000 00000 1 0010 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0x90,0x00]
+ tput rfsl0
+
+# CHECK: taput
+# BINARY: 011011 00000 00000 1 0011 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0x98,0x00]
+ taput rfsl0
+
+# CHECK: tcput
+# BINARY: 011011 00000 00000 1 0110 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xb0,0x00]
+ tcput rfsl0
+
+# CHECK: tcaput
+# BINARY: 011011 00000 00000 1 0111 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xb8,0x00]
+ tcaput rfsl0
+
+# CHECK: tnput
+# BINARY: 011011 00000 00000 1 1010 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xd0,0x00]
+ tnput rfsl0
+
+# CHECK: tnaput
+# BINARY: 011011 00000 00000 1 1011 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xd8,0x00]
+ tnaput rfsl0
+
+# CHECK: tncput
+# BINARY: 011011 00000 00000 1 1110 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xf0,0x00]
+ tncput rfsl0
+
+# CHECK: tncaput
+# BINARY: 011011 00000 00000 1 1111 0000000 0000
+# CHECK: encoding: [0x6c,0x00,0xf8,0x00]
+ tncaput rfsl0
+
+# CHECK: putd
+# BINARY: 010011 00000 00000 00001 1 0000 000000
+# CHECK: encoding: [0x4c,0x00,0x0c,0x00]
+ putd r0, r1
+
+# CHECK: aputd
+# BINARY: 010011 00000 00000 00001 1 0001 000000
+# CHECK: encoding: [0x4c,0x00,0x0c,0x40]
+ aputd r0, r1
+
+# CHECK: cputd
+# BINARY: 010011 00000 00000 00001 1 0100 000000
+# CHECK: encoding: [0x4c,0x00,0x0d,0x00]
+ cputd r0, r1
+
+# CHECK: caputd
+# BINARY: 010011 00000 00000 00001 1 0101 000000
+# CHECK: encoding: [0x4c,0x00,0x0d,0x40]
+ caputd r0, r1
+
+# CHECK: nputd
+# BINARY: 010011 00000 00000 00001 1 1000 000000
+# CHECK: encoding: [0x4c,0x00,0x0e,0x00]
+ nputd r0, r1
+
+# CHECK: naputd
+# BINARY: 010011 00000 00000 00001 1 1001 000000
+# CHECK: encoding: [0x4c,0x00,0x0e,0x40]
+ naputd r0, r1
+
+# CHECK: ncputd
+# BINARY: 010011 00000 00000 00001 1 1100 000000
+# CHECK: encoding: [0x4c,0x00,0x0f,0x00]
+ ncputd r0, r1
+
+# CHECK: ncaputd
+# BINARY: 010011 00000 00000 00001 1 1101 000000
+# CHECK: encoding: [0x4c,0x00,0x0f,0x40]
+ ncaputd r0, r1
+
+# CHECK: tputd
+# BINARY: 010011 00000 00000 00001 1 0010 000000
+# CHECK: encoding: [0x4c,0x00,0x0c,0x80]
+ tputd r1
+
+# CHECK: taputd
+# BINARY: 010011 00000 00000 00001 1 0011 000000
+# CHECK: encoding: [0x4c,0x00,0x0c,0xc0]
+ taputd r1
+
+# CHECK: tcputd
+# BINARY: 010011 00000 00000 00001 1 0110 000000
+# CHECK: encoding: [0x4c,0x00,0x0d,0x80]
+ tcputd r1
+
+# CHECK: tcaputd
+# BINARY: 010011 00000 00000 00001 1 0111 000000
+# CHECK: encoding: [0x4c,0x00,0x0d,0xc0]
+ tcaputd r1
+
+# CHECK: tnputd
+# BINARY: 010011 00000 00000 00001 1 1010 000000
+# CHECK: encoding: [0x4c,0x00,0x0e,0x80]
+ tnputd r1
+
+# CHECK: tnaputd
+# BINARY: 010011 00000 00000 00001 1 1011 000000
+# CHECK: encoding: [0x4c,0x00,0x0e,0xc0]
+ tnaputd r1
+
+# CHECK: tncputd
+# BINARY: 010011 00000 00000 00001 1 1110 000000
+# CHECK: encoding: [0x4c,0x00,0x0f,0x80]
+ tncputd r1
+
+# CHECK: tncaputd
+# BINARY: 010011 00000 00000 00001 1 1111 000000
+# CHECK: encoding: [0x4c,0x00,0x0f,0xc0]
+ tncaputd r1
+
# CHECK: get
# BINARY: 011011 00000 000000 00000 000000 0001
# CHECK: encoding: [0x6c,0x00,0x00,0x01]
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to make sure that all of the TYPE-A instructions supported by
+# the Microblaze can be parsed by the assembly parser.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 000000 00000 00000 00000 00000000000
+
+# CHECK: lbu
+# BINARY: 110000 00001 00010 00011 00000000000
+# CHECK: encoding: [0xc0,0x22,0x18,0x00]
+ lbu r1, r2, r3
+
+# CHECK: lbur
+# BINARY: 110000 00001 00010 00011 01000000000
+# CHECK: encoding: [0xc0,0x22,0x1a,0x00]
+ lbur r1, r2, r3
+
+# CHECK: lbui
+# BINARY: 111000 00001 00010 0000000000011100
+# CHECK: encoding: [0xe0,0x22,0x00,0x1c]
+ lbui r1, r2, 28
+
+# CHECK: lhu
+# BINARY: 110001 00001 00010 00011 00000000000
+# CHECK: encoding: [0xc4,0x22,0x18,0x00]
+ lhu r1, r2, r3
+
+# CHECK: lhur
+# BINARY: 110001 00001 00010 00011 01000000000
+# CHECK: encoding: [0xc4,0x22,0x1a,0x00]
+ lhur r1, r2, r3
+
+# CHECK: lhui
+# BINARY: 111001 00001 00010 0000000000011100
+# CHECK: encoding: [0xe4,0x22,0x00,0x1c]
+ lhui r1, r2, 28
+
+# CHECK: lw
+# BINARY: 110010 00001 00010 00011 00000000000
+# CHECK: encoding: [0xc8,0x22,0x18,0x00]
+ lw r1, r2, r3
+
+# CHECK: lwr
+# BINARY: 110010 00001 00010 00011 01000000000
+# CHECK: encoding: [0xc8,0x22,0x1a,0x00]
+ lwr r1, r2, r3
+
+# CHECK: lwi
+# BINARY: 111010 00001 00010 0000000000011100
+# CHECK: encoding: [0xe8,0x22,0x00,0x1c]
+ lwi r1, r2, 28
+
+# CHECK: lwx
+# BINARY: 110010 00001 00010 00011 10000000000
+# CHECK: encoding: [0xc8,0x22,0x1c,0x00]
+ lwx r1, r2, r3
+
+# CHECK: sb
+# BINARY: 110100 00001 00010 00011 00000000000
+# CHECK: encoding: [0xd0,0x22,0x18,0x00]
+ sb r1, r2, r3
+
+# CHECK: sbr
+# BINARY: 110100 00001 00010 00011 01000000000
+# CHECK: encoding: [0xd0,0x22,0x1a,0x00]
+ sbr r1, r2, r3
+
+# CHECK: sbi
+# BINARY: 111100 00001 00010 0000000000011100
+# CHECK: encoding: [0xf0,0x22,0x00,0x1c]
+ sbi r1, r2, 28
+
+# CHECK: sh
+# BINARY: 110101 00001 00010 00011 00000000000
+# CHECK: encoding: [0xd4,0x22,0x18,0x00]
+ sh r1, r2, r3
+
+# CHECK: shr
+# BINARY: 110101 00001 00010 00011 01000000000
+# CHECK: encoding: [0xd4,0x22,0x1a,0x00]
+ shr r1, r2, r3
+
+# CHECK: shi
+# BINARY: 111101 00001 00010 0000000000011100
+# CHECK: encoding: [0xf4,0x22,0x00,0x1c]
+ shi r1, r2, 28
+
+# CHECK: sw
+# BINARY: 110110 00001 00010 00011 00000000000
+# CHECK: encoding: [0xd8,0x22,0x18,0x00]
+ sw r1, r2, r3
+
+# CHECK: swr
+# BINARY: 110110 00001 00010 00011 01000000000
+# CHECK: encoding: [0xd8,0x22,0x1a,0x00]
+ swr r1, r2, r3
+
+# CHECK: swi
+# BINARY: 111110 00001 00010 0000000000011100
+# CHECK: encoding: [0xf8,0x22,0x00,0x1c]
+ swi r1, r2, 28
+
+# CHECK: swx
+# BINARY: 110110 00001 00010 00011 10000000000
+# CHECK: encoding: [0xd8,0x22,0x1c,0x00]
+ swx r1, r2, r3
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to ensure that all FPU instructions can be parsed by the
+# assembly parser correctly.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 011011 00000 00000 00000 00000000000
+
+# CHECK: pcmpbf
+# BINARY: 100000 00000 00001 00010 10000000000
+# CHECK: encoding: [0x80,0x01,0x14,0x00]
+ pcmpbf r0, r1, r2
+
+# CHECK: pcmpeq
+# BINARY: 100011 00000 00001 00010 10000000000
+# CHECK: encoding: [0x8c,0x01,0x14,0x00]
+ pcmpeq r0, r1, r2
+
+# CHECK: pcmpne
+# BINARY: 100010 00000 00001 00010 10000000000
+# CHECK: encoding: [0x88,0x01,0x14,0x00]
+ pcmpne r0, r1, r2
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to make sure that all of the TYPE-A instructions supported by
+# the Microblaze can be parsed by the assembly parser.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 000000 00000 00000 00000 00000000000
+
+# CHECK: bsrl
+# BINARY: 010001 00001 00010 00011 00000000000
+# CHECK: encoding: [0x44,0x22,0x18,0x00]
+ bsrl r1, r2, r3
+
+# CHECK: bsra
+# BINARY: 010001 00001 00010 00011 01000000000
+# CHECK: encoding: [0x44,0x22,0x1a,0x00]
+ bsra r1, r2, r3
+
+# CHECK: bsll
+# BINARY: 010001 00001 00010 00011 10000000000
+# CHECK: encoding: [0x44,0x22,0x1c,0x00]
+ bsll r1, r2, r3
+
+# CHECK: bsrli
+# BINARY: 011001 00001 00010 0000000000000000
+# CHECK: encoding: [0x64,0x22,0x00,0x00]
+ bsrli r1, r2, 0
+
+# CHECK: bsrai
+# BINARY: 011001 00001 00010 0000001000000000
+# CHECK: encoding: [0x64,0x22,0x02,0x00]
+ bsrai r1, r2, 0
+
+# CHECK: bslli
+# BINARY: 011001 00001 00010 0000010000000000
+# CHECK: encoding: [0x64,0x22,0x04,0x00]
+ bslli r1, r2, 0
+
+# CHECK: sra
+# BINARY: 100100 00001 00010 00000 00000000001
+# CHECK: encoding: [0x90,0x22,0x00,0x01]
+ sra r1, r2
+
+# CHECK: srl
+# BINARY: 100100 00001 00010 00000 00001000001
+# CHECK: encoding: [0x90,0x22,0x00,0x41]
+ srl r1, r2
--- /dev/null
+# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
+
+# Test to ensure that all FPU instructions can be parsed by the
+# assembly parser correctly.
+
+# TYPE A: OPCODE RD RA RB FLAGS
+# BINARY: 011011 00000 00000 00000 00000000000
+
+# CHECK: mfs
+# BINARY: 100101 00000 00000 10000 00000000000
+# CHECK: encoding: [0x94,0x00,0x80,0x00]
+ mfs r0, 0x0
+
+# CHECK: msrclr
+# BINARY: 100101 00000 100010 000000000000000
+# CHECK: encoding: [0x94,0x11,0x00,0x00]
+ msrclr r0, 0x0
+
+# CHECK: msrset
+# BINARY: 100101 00000 100000 000000000000000
+# CHECK: encoding: [0x94,0x10,0x00,0x00]
+ msrset r0, 0x0
+
+# CHECK: mts
+# BINARY: 100101 00000 00000 11 00000000000000
+# CHECK: encoding: [0x94,0x00,0xc0,0x00]
+ mts 0x0 , r0
+
+# CHECK: wdc
+# BINARY: 100100 00000 00000 00001 00001100100
+# CHECK: encoding: [0x90,0x00,0x08,0x64]
+ wdc r0, r1
+
+# CHECK: wdc.clear
+# BINARY: 100100 00000 00000 00001 00001100110
+# CHECK: encoding: [0x90,0x00,0x08,0x66]
+ wdc.clear r0, r1
+
+# CHECK: wdc.flush
+# BINARY: 100100 00000 00000 00001 00001110100
+# CHECK: encoding: [0x90,0x00,0x08,0x74]
+ wdc.flush r0, r1
+
+# CHECK: wic
+# BINARY: 100100 00000 00000 00001 00001101000
+# CHECK: encoding: [0x90,0x00,0x08,0x68]
+ wic r0, r1
# CHECK: encoding: [0x8c,0x22,0x18,0x00]
andn r1, r2, r3
-# CHECK: beq
-# BINARY: 100111 00000 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0x02,0x18,0x00]
- beq r2, r3
-
-# CHECK: bge
-# BINARY: 100111 00101 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0xa2,0x18,0x00]
- bge r2, r3
-
-# CHECK: bgt
-# BINARY: 100111 00100 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0x82,0x18,0x00]
- bgt r2, r3
-
-# CHECK: ble
-# BINARY: 100111 00011 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0x62,0x18,0x00]
- ble r2, r3
-
-# CHECK: blt
-# BINARY: 100111 00010 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0x42,0x18,0x00]
- blt r2, r3
-
-# CHECK: bne
-# BINARY: 100111 00001 00010 00011 00000000000
-# CHECK: encoding: [0x9c,0x22,0x18,0x00]
- bne r2, r3
+# CHECK: cmp
+# BINARY: 000101 00001 00010 00011 00000000001
+# CHECK: encoding: [0x14,0x22,0x18,0x01]
+ cmp r1, r2, r3
+
+# CHECK: cmpu
+# BINARY: 000101 00001 00010 00011 00000000011
+# CHECK: encoding: [0x14,0x22,0x18,0x03]
+ cmpu r1, r2, r3
+
+# CHECK: idiv
+# BINARY: 010010 00001 00010 00011 00000000000
+# CHECK: encoding: [0x48,0x22,0x18,0x00]
+ idiv r1, r2, r3
+
+# CHECK: idivu
+# BINARY: 010010 00001 00010 00011 00000000010
+# CHECK: encoding: [0x48,0x22,0x18,0x02]
+ idivu r1, r2, r3
+
+# CHECK: mul
+# BINARY: 010000 00001 00010 00011 00000000000
+# CHECK: encoding: [0x40,0x22,0x18,0x00]
+ mul r1, r2, r3
+
+# CHECK: mulh
+# BINARY: 010000 00001 00010 00011 00000000001
+# CHECK: encoding: [0x40,0x22,0x18,0x01]
+ mulh r1, r2, r3
+
+# CHECK: mulhu
+# BINARY: 010000 00001 00010 00011 00000000011
+# CHECK: encoding: [0x40,0x22,0x18,0x03]
+ mulhu r1, r2, r3
+
+# CHECK: mulhsu
+# BINARY: 010000 00001 00010 00011 00000000010
+# CHECK: encoding: [0x40,0x22,0x18,0x02]
+ mulhsu r1, r2, r3
+
+# CHECK: or
+# BINARY: 100000 00001 00010 00011 00000000000
+# CHECK: encoding: [0x80,0x22,0x18,0x00]
+ or r1, r2, r3
+
+# FIXMEC: rsub
+# BINARY: 000001 00001 00010 00011 00000000000
+# FIXMEC: encoding: [0x04,0x22,0x18,0x00]
+ rsub r1, r2, r3
+
+# FIXMEC: rsubc
+# BINARY: 000011 00001 00010 00011 00000000000
+# FIXMEC: encoding: [0x0c,0x22,0x18,0x00]
+ rsubc r1, r2, r3
+
+# FIXMEC: rsubk
+# BINARY: 000101 00001 00010 00011 00000000000
+# FIXMEC: encoding: [0x14,0x22,0x18,0x00]
+ rsubk r1, r2, r3
+
+# FIXMEC: rsubkc
+# BINARY: 000111 00001 00010 00011 00000000000
+# FIXMEC: encoding: [0x1c,0x22,0x18,0x00]
+ rsubkc r1, r2, r3
+
+# CHECK: sext16
+# BINARY: 100100 00001 00010 00000 00001100001
+# CHECK: encoding: [0x90,0x22,0x00,0x61]
+ sext16 r1, r2
+
+# CHECK: sext8
+# BINARY: 100100 00001 00010 00000 00001100000
+# CHECK: encoding: [0x90,0x22,0x00,0x60]
+ sext8 r1, r2
+
+# CHECK: xor
+# BINARY: 100010 00001 00010 00011 00000000000
+# CHECK: encoding: [0x88,0x22,0x18,0x00]
+ xor r1, r2, r3
# CHECK: nop
# BINARY: 100000 00000 00000 00000 00000000000
projects / oota-llvm.git / commitdiff