This makes it possible to just use a zero value to represent "no pass", so
the phony NoPassID global variable is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568
91177308-0d34-0410-b5e6-
96231b3b80d8
// createCustomMachineSched);
//
// Inside <Target>PassConfig:
// createCustomMachineSched);
//
// Inside <Target>PassConfig:
-// enablePass(MachineSchedulerID);
+// enablePass(&MachineSchedulerID);
// MachineSchedRegistry::setDefault(createCustomMachineSched);
//
//===----------------------------------------------------------------------===//
// MachineSchedRegistry::setDefault(createCustomMachineSched);
//
//===----------------------------------------------------------------------===//
-extern char &NoPassID; // Allow targets to choose not to run a pass.
-
class PassConfigImpl;
/// Target-Independent Code Generator Pass Configuration Options.
class PassConfigImpl;
/// Target-Independent Code Generator Pass Configuration Options.
/// Allow the target to override a specific pass without overriding the pass
/// pipeline. When passes are added to the standard pipeline at the
/// Allow the target to override a specific pass without overriding the pass
/// pipeline. When passes are added to the standard pipeline at the
- /// point where StadardID is expected, add TargetID in its place.
- void substitutePass(char &StandardID, char &TargetID);
+ /// point where StandardID is expected, add TargetID in its place.
+ void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
/// Insert InsertedPassID pass after TargetPassID pass.
/// Insert InsertedPassID pass after TargetPassID pass.
- void insertPass(const char &TargetPassID, const char &InsertedPassID);
+ void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
/// Allow the target to enable a specific standard pass by default.
/// Allow the target to enable a specific standard pass by default.
- void enablePass(char &ID) { substitutePass(ID, ID); }
+ void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
/// Allow the target to disable a specific standard pass by default.
/// Allow the target to disable a specific standard pass by default.
- void disablePass(char &ID) { substitutePass(ID, NoPassID); }
+ void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
- /// Return the pass ssubtituted for StandardID by the target.
+ /// Return the pass substituted for StandardID by the target.
/// If no substitution exists, return StandardID.
AnalysisID getPassSubstitution(AnalysisID StandardID) const;
/// If no substitution exists, return StandardID.
AnalysisID getPassSubstitution(AnalysisID StandardID) const;
///
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
///
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
- /// Return the pass that was added, or NoPassID.
- AnalysisID addPass(char &ID);
+ /// Return the pass that was added, or zero if no pass was added.
+ AnalysisID addPass(AnalysisID PassID);
/// Add a pass to the PassManager.
void addPass(Pass *P);
/// Add a pass to the PassManager.
void addPass(Pass *P);
/// simple binary flags that either suppress the pass or do nothing.
/// i.e. -disable-mypass=false has no effect.
/// These should be converted to boolOrDefault in order to use applyOverride.
/// simple binary flags that either suppress the pass or do nothing.
/// i.e. -disable-mypass=false has no effect.
/// These should be converted to boolOrDefault in order to use applyOverride.
-static AnalysisID applyDisable(AnalysisID ID, bool Override) {
+static AnalysisID applyDisable(AnalysisID PassID, bool Override) {
- return &NoPassID;
- return ID;
+ return 0;
+ return PassID;
}
/// Allow Pass selection to be overriden by command line options. This supports
}
/// Allow Pass selection to be overriden by command line options. This supports
case cl::BOU_UNSET:
return TargetID;
case cl::BOU_TRUE:
case cl::BOU_UNSET:
return TargetID;
case cl::BOU_TRUE:
- if (TargetID != &NoPassID)
- if (StandardID == &NoPassID)
report_fatal_error("Target cannot enable pass");
return StandardID;
case cl::BOU_FALSE:
report_fatal_error("Target cannot enable pass");
return StandardID;
case cl::BOU_FALSE:
}
llvm_unreachable("Invalid command line option state");
}
}
llvm_unreachable("Invalid command line option state");
}
"Target Pass Configuration", false, false)
char TargetPassConfig::ID = 0;
"Target Pass Configuration", false, false)
char TargetPassConfig::ID = 0;
-static char NoPassIDAnchor = 0;
-char &llvm::NoPassID = NoPassIDAnchor;
-
// Pseudo Pass IDs.
char TargetPassConfig::EarlyTailDuplicateID = 0;
char TargetPassConfig::PostRAMachineLICMID = 0;
// Pseudo Pass IDs.
char TargetPassConfig::EarlyTailDuplicateID = 0;
char TargetPassConfig::PostRAMachineLICMID = 0;
// that are part of a standard pass pipeline without overridding the entire
// pipeline. This mechanism allows target options to inherit a standard pass's
// user interface. For example, a target may disable a standard pass by
// that are part of a standard pass pipeline without overridding the entire
// pipeline. This mechanism allows target options to inherit a standard pass's
// user interface. For example, a target may disable a standard pass by
- // default by substituting NoPass, and the user may still enable that standard
- // pass with an explicit command line option.
+ // default by substituting a pass ID of zero, and the user may still enable
+ // that standard pass with an explicit command line option.
DenseMap<AnalysisID,AnalysisID> TargetPasses;
/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
DenseMap<AnalysisID,AnalysisID> TargetPasses;
/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
initializeCodeGen(*PassRegistry::getPassRegistry());
// Substitute Pseudo Pass IDs for real ones.
initializeCodeGen(*PassRegistry::getPassRegistry());
// Substitute Pseudo Pass IDs for real ones.
- substitutePass(EarlyTailDuplicateID, TailDuplicateID);
- substitutePass(PostRAMachineLICMID, MachineLICMID);
+ substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
+ substitutePass(&PostRAMachineLICMID, &MachineLICMID);
// Temporarily disable experimental passes.
// Temporarily disable experimental passes.
- substitutePass(MachineSchedulerID, NoPassID);
+ substitutePass(&MachineSchedulerID, 0);
}
/// Insert InsertedPassID pass after TargetPassID.
}
/// Insert InsertedPassID pass after TargetPassID.
-void TargetPassConfig::insertPass(const char &TargetPassID,
- const char &InsertedPassID) {
- assert(&TargetPassID != &InsertedPassID && "Insert a pass after itself!");
- std::pair<AnalysisID, AnalysisID> P(&TargetPassID, &InsertedPassID);
+void TargetPassConfig::insertPass(AnalysisID TargetPassID,
+ AnalysisID InsertedPassID) {
+ assert(TargetPassID != InsertedPassID && "Insert a pass after itself!");
+ std::pair<AnalysisID, AnalysisID> P(TargetPassID, InsertedPassID);
Impl->InsertedPasses.push_back(P);
}
Impl->InsertedPasses.push_back(P);
}
-void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
- Impl->TargetPasses[&StandardID] = &TargetID;
+void TargetPassConfig::substitutePass(AnalysisID StandardID,
+ AnalysisID TargetID) {
+ Impl->TargetPasses[StandardID] = TargetID;
}
AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
}
AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
/// Add a CodeGen pass at this point in the pipeline after checking for target
/// and command line overrides.
/// Add a CodeGen pass at this point in the pipeline after checking for target
/// and command line overrides.
-AnalysisID TargetPassConfig::addPass(char &ID) {
+AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
assert(!Initialized && "PassConfig is immutable");
assert(!Initialized && "PassConfig is immutable");
- AnalysisID TargetID = getPassSubstitution(&ID);
- AnalysisID FinalID = overridePass(&ID, TargetID);
- if (FinalID == &NoPassID)
+ AnalysisID TargetID = getPassSubstitution(PassID);
+ AnalysisID FinalID = overridePass(PassID, TargetID);
+ if (FinalID == 0)
return FinalID;
Pass *P = Pass::createPass(FinalID);
return FinalID;
Pass *P = Pass::createPass(FinalID);
for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
I != E; ++I) {
for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
I != E; ++I) {
- if ((*I).first == &ID) {
+ if ((*I).first == PassID) {
assert((*I).second && "Illegal Pass ID!");
Pass *NP = Pass::createPass((*I).second);
assert(NP && "Pass ID not registered");
assert((*I).second && "Illegal Pass ID!");
Pass *NP = Pass::createPass((*I).second);
assert(NP && "Pass ID not registered");
assert (TPI && IPI && "Pass ID not registered!");
const char *TID = (char *)(TPI->getTypeInfo());
const char *IID = (char *)(IPI->getTypeInfo());
assert (TPI && IPI && "Pass ID not registered!");
const char *TID = (char *)(TPI->getTypeInfo());
const char *IID = (char *)(IPI->getTypeInfo());
- insertPass(*TID, *IID);
}
// Expand pseudo-instructions emitted by ISel.
}
// Expand pseudo-instructions emitted by ISel.
- addPass(ExpandISelPseudosID);
+ addPass(&ExpandISelPseudosID);
// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
else {
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
else {
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
- addPass(LocalStackSlotAllocationID);
+ addPass(&LocalStackSlotAllocationID);
printAndVerify("After PostRegAlloc passes");
// Insert prolog/epilog code. Eliminate abstract frame index references...
printAndVerify("After PostRegAlloc passes");
// Insert prolog/epilog code. Eliminate abstract frame index references...
- addPass(PrologEpilogCodeInserterID);
+ addPass(&PrologEpilogCodeInserterID);
printAndVerify("After PrologEpilogCodeInserter");
/// Add passes that optimize machine instructions after register allocation.
printAndVerify("After PrologEpilogCodeInserter");
/// Add passes that optimize machine instructions after register allocation.
addMachineLateOptimization();
// Expand pseudo instructions before second scheduling pass.
addMachineLateOptimization();
// Expand pseudo instructions before second scheduling pass.
- addPass(ExpandPostRAPseudosID);
+ addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
- addPass(PostRASchedulerID);
+ addPass(&PostRASchedulerID);
printAndVerify("After PostRAScheduler");
}
// GC
printAndVerify("After PostRAScheduler");
}
// GC
- addPass(GCMachineCodeAnalysisID);
+ addPass(&GCMachineCodeAnalysisID);
if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs()));
if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs()));
/// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
/// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
- if (addPass(EarlyTailDuplicateID) != &NoPassID)
+ if (addPass(&EarlyTailDuplicateID))
printAndVerify("After Pre-RegAlloc TailDuplicate");
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
printAndVerify("After Pre-RegAlloc TailDuplicate");
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
- addPass(OptimizePHIsID);
+ addPass(&OptimizePHIsID);
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
- addPass(LocalStackSlotAllocationID);
+ addPass(&LocalStackSlotAllocationID);
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
- addPass(DeadMachineInstructionElimID);
+ addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen DCE pass");
printAndVerify("After codegen DCE pass");
- addPass(MachineLICMID);
- addPass(MachineCSEID);
- addPass(MachineSinkingID);
+ addPass(&MachineLICMID);
+ addPass(&MachineCSEID);
+ addPass(&MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
printAndVerify("After Machine LICM, CSE and Sinking passes");
- addPass(PeepholeOptimizerID);
+ addPass(&PeepholeOptimizerID);
printAndVerify("After codegen peephole optimization pass");
}
printAndVerify("After codegen peephole optimization pass");
}
/// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
/// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
- addPass(PHIEliminationID);
- addPass(TwoAddressInstructionPassID);
+ addPass(&PHIEliminationID);
+ addPass(&TwoAddressInstructionPassID);
addPass(RegAllocPass);
printAndVerify("After Register Allocation");
addPass(RegAllocPass);
printAndVerify("After Register Allocation");
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
- addPass(ProcessImplicitDefsID);
+ addPass(&ProcessImplicitDefsID);
// LiveVariables currently requires pure SSA form.
//
// LiveVariables currently requires pure SSA form.
//
// LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them).
// LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them).
- addPass(LiveVariablesID);
+ addPass(&LiveVariablesID);
// Add passes that move from transformed SSA into conventional SSA. This is a
// "copy coalescing" problem.
//
if (!EnableStrongPHIElim) {
// Edge splitting is smarter with machine loop info.
// Add passes that move from transformed SSA into conventional SSA. This is a
// "copy coalescing" problem.
//
if (!EnableStrongPHIElim) {
// Edge splitting is smarter with machine loop info.
- addPass(MachineLoopInfoID);
- addPass(PHIEliminationID);
+ addPass(&MachineLoopInfoID);
+ addPass(&PHIEliminationID);
- addPass(TwoAddressInstructionPassID);
+ addPass(&TwoAddressInstructionPassID);
- addPass(StrongPHIEliminationID);
+ addPass(&StrongPHIEliminationID);
- addPass(RegisterCoalescerID);
+ addPass(&RegisterCoalescerID);
// PreRA instruction scheduling.
// PreRA instruction scheduling.
- if (addPass(MachineSchedulerID) != &NoPassID)
+ if (addPass(&MachineSchedulerID))
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
printAndVerify("After pre-rewrite passes");
// Finally rewrite virtual registers.
printAndVerify("After pre-rewrite passes");
// Finally rewrite virtual registers.
- addPass(VirtRegRewriterID);
+ addPass(&VirtRegRewriterID);
printAndVerify("After Virtual Register Rewriter");
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
printAndVerify("After Virtual Register Rewriter");
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
//
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
//
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
- addPass(StackSlotColoringID);
+ addPass(&StackSlotColoringID);
// Run post-ra machine LICM to hoist reloads / remats.
//
// FIXME: can this move into MachineLateOptimization?
// Run post-ra machine LICM to hoist reloads / remats.
//
// FIXME: can this move into MachineLateOptimization?
- addPass(PostRAMachineLICMID);
+ addPass(&PostRAMachineLICMID);
printAndVerify("After StackSlotColoring and postra Machine LICM");
}
printAndVerify("After StackSlotColoring and postra Machine LICM");
}
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion.
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (addPass(BranchFolderPassID) != &NoPassID)
+ if (addPass(&BranchFolderPassID))
printAndVerify("After BranchFolding");
// Tail duplication.
printAndVerify("After BranchFolding");
// Tail duplication.
- if (addPass(TailDuplicateID) != &NoPassID)
+ if (addPass(&TailDuplicateID))
printAndVerify("After TailDuplicate");
// Copy propagation.
printAndVerify("After TailDuplicate");
// Copy propagation.
- if (addPass(MachineCopyPropagationID) != &NoPassID)
+ if (addPass(&MachineCopyPropagationID))
printAndVerify("After copy propagation pass");
}
/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
printAndVerify("After copy propagation pass");
}
/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
- AnalysisID ID = &NoPassID;
if (!DisableBlockPlacement) {
// MachineBlockPlacement is a new pass which subsumes the functionality of
// CodPlacementOpt. The old code placement pass can be restored by
// disabling block placement, but eventually it will be removed.
if (!DisableBlockPlacement) {
// MachineBlockPlacement is a new pass which subsumes the functionality of
// CodPlacementOpt. The old code placement pass can be restored by
// disabling block placement, but eventually it will be removed.
- ID = addPass(MachineBlockPlacementID);
+ PassID = addPass(&MachineBlockPlacementID);
- ID = addPass(CodePlacementOptID);
+ PassID = addPass(&CodePlacementOptID);
// Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats)
// Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats)
- addPass(MachineBlockPlacementStatsID);
+ addPass(&MachineBlockPlacementStatsID);
printAndVerify("After machine block placement.");
}
printAndVerify("After machine block placement.");
}
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
- addPass(IfConverterID);
+ addPass(&IfConverterID);
}
if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass());
}
if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass());
addPass(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
addPass(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
- addPass(UnpackMachineBundlesID);
+ addPass(&UnpackMachineBundlesID);
}
addPass(createARMConstantIslandPass());
}
addPass(createARMConstantIslandPass());
bool HexagonPassConfig::addPreSched2() {
bool HexagonPassConfig::addPreSched2() {
- addPass(IfConverterID);
+ addPass(&IfConverterID);