[PowerPC] Correct P7 dispatch unit allocation for vector instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205222 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCScheduleP7.td b/lib/Target/PowerPC/PPCScheduleP7.td
index 04d37e4051a8f0c1c00cd1ee6e0c7135cac8e730..d3e426975ec0a1fb8bb4a557bd44256faa8628ff 100644 (file)
--- a/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/lib/Target/PowerPC/PPCScheduleP7.td
@@ -339,36 +339,28 @@ def P7Itineraries : ProcessorItineraries<
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [5, 1, 1]>,
-  InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [7, 1, 1]>,
-  InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
                                    InstrStage<1, [P7_VS2]>],
                                   [3, 1, 1]>
 ]>;