[X86][SSE] Vector integer to float conversion memory folding

Added missing memory folding for the (V)CVTDQ2PS instructions - we can safely fold these (but not the (V)CVTDQ2PD versions which have a register/memory size discrepancy in the source operand). I've added a test case demonstrating that stack folding now works.

Differential Revision: http://reviews.llvm.org/D5981

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221407 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 4e05c7c2d2e6042c8a4f53e9dd8d7230a1147a9c..dd463f15b32e7b4ac9ee8239e4e14bfd5fb20d79 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -448,6 +448,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
+    { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
@@ -526,6 +527,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
+    { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
@@ -559,6 +561,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
 
     // AVX 256-bit foldable instructions
+    { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },

diff --git a/test/CodeGen/X86/avx1-stack-reload-folding.ll b/test/CodeGen/X86/avx1-stack-reload-folding.ll
index 5da1b4c57674165b6ab01d183a7c79e3bfa870b7..7b232026ec1008a358727a384124065896054509 100644 (file)
--- a/test/CodeGen/X86/avx1-stack-reload-folding.ll
+++ b/test/CodeGen/X86/avx1-stack-reload-folding.ll
@@ -3,14 +3,32 @@
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"\r
 target triple = "x86_64-unknown-unknown"\r
 \r
-; Function Attrs: nounwind readonly uwtable\r
-define <32 x double> @_Z14vstack_foldDv32_dS_(<32 x double> %a, <32 x double> %b) #0 {\r
-  %1 = fadd <32 x double> %a, %b\r
-  %2 = fsub <32 x double> %a, %b\r
-  %3 = fmul <32 x double> %1, %2\r
-  ret <32 x double> %3\r
+; Stack reload folding tests - we use the 'big vectors' pattern to guarantee spilling to stack.\r
+;\r
+; Many of these tests are primarily to check memory folding with specific instructions. Using a basic\r
+; load/cvt/store pattern to test for this would mean that it wouldn't be the memory folding code thats\r
+; being tested - the load-execute version of the instruction from the tables would be matched instead.\r
 \r
-  ;CHECK-NOT:  vmovapd {{.*#+}} 32-byte Reload\r
+define void @stack_fold_vmulpd(<64 x double>* %a, <64 x double>* %b, <64 x double>* %c) {\r
   ;CHECK:       vmulpd {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
-  ;CHECK-NOT:  vmovapd {{.*#+}} 32-byte Reload\r
+  %1 = load <64 x double>* %a\r
+  %2 = load <64 x double>* %b\r
+  %3 = fadd <64 x double> %1, %2\r
+  %4 = fsub <64 x double> %1, %2\r
+  %5 = fmul <64 x double> %3, %4\r
+  store <64 x double> %5, <64 x double>* %c\r
+  ret void\r
+}\r
+\r
+define void @stack_fold_cvtdq2ps(<128 x i32>* %a, <128 x i32>* %b, <128 x float>* %c) {\r
+  ;CHECK:   vcvtdq2ps {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
+  %1 = load <128 x i32>* %a\r
+  %2 = load <128 x i32>* %b\r
+  %3 = and <128 x i32> %1, %2\r
+  %4 = xor <128 x i32> %1, %2\r
+  %5 = sitofp <128 x i32> %3 to <128 x float>\r
+  %6 = sitofp <128 x i32> %4 to <128 x float>\r
+  %7 = fadd <128 x float> %5, %6\r
+  store <128 x float> %7, <128 x float>* %c\r
+  ret void\r
 }\r