The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143996
91177308-0d34-0410-b5e6-
96231b3b80d8
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
switch (MI->getOpcode()) {
case X86::V_SET0:
- return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr));
+ return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
case X86::TEST8ri_NOREX:
MI->setDesc(get(X86::TEST8ri));
return true;
define void @zero128() nounwind ssp {
entry:
- ; CHECK: vpxor
+ ; CHECK: vxorps
; CHECK: vmovaps
store <4 x float> zeroinitializer, <4 x float>* @z, align 16
ret void
ret void
}
+; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the
+; mixed domains here.
; CHECK: vsel_i64
-; CHECK: pxor
+; CHECK: xorps
; CHECK: pand
; CHECK: andnps
; CHECK: orps
ret void
}
+; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the
+; mixed domains here.
; CHECK: vsel_double
-; CHECK: pxor
+; CHECK: xorps
; CHECK: pand
; CHECK: andnps
; CHECK: orps
ret void
; CHECK: test7:
-; CHECK: pxor %xmm0, %xmm0
+; CHECK: xorps %xmm0, %xmm0
; CHECK: movaps %xmm0, 0
}
-; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
-; RUN: grep pxor %t | count 1
-; RUN: grep movaps %t | count 1
-; RUN: not grep shuf %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; Without any typed operations, always use the smaller xorps.
+; CHECK: test
+; CHECK: xorps
define <2 x double> @test() {
ret <2 x double> zeroinitializer
}
+; Prefer a constant pool load here.
+; CHECK: test2
+; CHECK-NOT: shuf
+; CHECK: movaps LCP
+; CHECK-NEXT: ret
define <4 x i32> @test2() nounwind {
ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 >
}
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; CHECK: foo
; CHECK: xorps
define void @foo(<4 x float>* %P) {
%T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
ret void
}
+; CHECK: bar
; CHECK: pxor
define void @bar(<4 x i32>* %P) {
%T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1]
ret void
}
+; Without any type hints from operations, we fall back to the smaller xorps.
+; The IR type <4 x i32> is ignored.
+; CHECK: untyped_zero
+; CHECK: xorps
+; CHECK: movaps
+define void @untyped_zero(<4 x i32>* %p) {
+entry:
+ store <4 x i32> zeroinitializer, <4 x i32>* %p, align 16
+ ret void
+}
-; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 1
; 64-bit stores here do not use MMX.
ret <4 x i32> %tmp
; X32: test1:
-; X32: pxor %xmm0, %xmm0
+; X32: xorps %xmm0, %xmm0
; X32: ret
}