Ensure bitcode encoding of instructions and their operands stays stable.

This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls.

Work was done by lama.saba@intel.com.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202647 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Bitcode/memInstructions.3.2.ll b/test/Bitcode/memInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..868e4b5
--- /dev/null
+++ b/test/Bitcode/memInstructions.3.2.ll
@@ -0,0 +1,308 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread memory related instructions of\r
+; older bitcode files.\r
+\r
+define void @alloca(){\r
+entry:\r
+; CHECK: %res1 = alloca i8\r
+  %res1 = alloca i8\r
+  \r
+; CHECK-NEXT: %res2 = alloca i8, i32 2\r
+  %res2 = alloca i8, i32 2\r
+\r
+; CHECK-NEXT: %res3 = alloca i8, i32 2, align 4\r
+  %res3 = alloca i8, i32 2, align 4\r
+  \r
+; CHECK-NEXT: %res4 = alloca i8, align 4\r
+  %res4 = alloca i8, align 4\r
+  \r
+  ret void\r
+}\r
+\r
+define void @load(){\r
+entry:\r
+  %ptr1 = alloca i8\r
+  store i8 2, i8* %ptr1\r
+  \r
+; CHECK: %res1 = load i8* %ptr1\r
+  %res1 = load i8* %ptr1\r
+  \r
+; CHECK-NEXT: %res2 = load volatile i8* %ptr1\r
+  %res2 = load volatile i8* %ptr1\r
+  \r
+; CHECK-NEXT: %res3 = load i8* %ptr1, align 1\r
+  %res3 = load i8* %ptr1, align 1\r
+  \r
+; CHECK-NEXT: %res4 = load volatile i8* %ptr1, align 1\r
+  %res4 = load volatile i8* %ptr1, align 1\r
+  \r
+; CHECK-NEXT: %res5 = load i8* %ptr1, !nontemporal !0\r
+  %res5 = load i8* %ptr1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: %res6 = load volatile i8* %ptr1, !nontemporal !0\r
+  %res6 = load volatile i8* %ptr1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: %res7 = load i8* %ptr1, align 1, !nontemporal !0\r
+  %res7 = load i8* %ptr1, align 1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0\r
+  %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: %res9 = load i8* %ptr1, !invariant.load !1\r
+  %res9 = load i8* %ptr1, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res10 = load volatile i8* %ptr1, !invariant.load !1\r
+  %res10 = load volatile i8* %ptr1, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1\r
+  %res11 = load i8* %ptr1, align 1, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1\r
+  %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res13 = load i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}\r
+  %res13 = load i8* %ptr1, !nontemporal !0, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res14 = load volatile i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}\r
+  %res14 = load volatile i8* %ptr1, !nontemporal !0, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res15 = load i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}\r
+  %res15 = load i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1\r
+  \r
+; CHECK-NEXT: %res16 = load volatile i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}\r
+  %res16 = load volatile i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @loadAtomic(){\r
+entry:\r
+  %ptr1 = alloca i8\r
+  store i8 2, i8* %ptr1\r
+  \r
+; CHECK: %res1 = load atomic i8* %ptr1 unordered, align 1\r
+  %res1 = load atomic i8* %ptr1 unordered, align 1\r
+  \r
+; CHECK-NEXT: %res2 = load atomic i8* %ptr1 monotonic, align 1\r
+  %res2 = load atomic i8* %ptr1 monotonic, align 1\r
+  \r
+; CHECK-NEXT: %res3 = load atomic i8* %ptr1 acquire, align 1\r
+  %res3 = load atomic i8* %ptr1 acquire, align 1\r
+  \r
+; CHECK-NEXT: %res4 = load atomic i8* %ptr1 seq_cst, align 1\r
+  %res4 = load atomic i8* %ptr1 seq_cst, align 1\r
+  \r
+; CHECK-NEXT: %res5 = load atomic volatile i8* %ptr1 unordered, align 1\r
+  %res5 = load atomic volatile i8* %ptr1 unordered, align 1\r
+  \r
+; CHECK-NEXT: %res6 = load atomic volatile i8* %ptr1 monotonic, align 1\r
+  %res6 = load atomic volatile i8* %ptr1 monotonic, align 1\r
+  \r
+; CHECK-NEXT: %res7 = load atomic volatile i8* %ptr1 acquire, align 1\r
+  %res7 = load atomic volatile i8* %ptr1 acquire, align 1\r
+  \r
+; CHECK-NEXT: %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1\r
+  %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1\r
+  \r
+; CHECK-NEXT: %res9 = load atomic i8* %ptr1 singlethread unordered, align 1\r
+  %res9 = load atomic i8* %ptr1 singlethread unordered, align 1\r
+  \r
+; CHECK-NEXT: %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1\r
+  %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1\r
+  \r
+; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1\r
+  %res11 = load atomic i8* %ptr1 singlethread acquire, align 1\r
+  \r
+; CHECK-NEXT: %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1\r
+  %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1\r
+  \r
+; CHECK-NEXT: %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1\r
+  %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1\r
+  \r
+; CHECK-NEXT: %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1\r
+  %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1\r
+  \r
+; CHECK-NEXT: %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1\r
+  %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1\r
+  \r
+; CHECK-NEXT: %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1\r
+  %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @store(){\r
+entry:\r
+  %ptr1 = alloca i8\r
+  \r
+; CHECK: store i8 2, i8* %ptr1\r
+  store i8 2, i8* %ptr1\r
+  \r
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1\r
+  store volatile i8 2, i8* %ptr1\r
+  \r
+; CHECK-NEXT: store i8 2, i8* %ptr1, align 1\r
+  store i8 2, i8* %ptr1, align 1\r
+  \r
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1\r
+  store volatile i8 2, i8* %ptr1, align 1\r
+  \r
+; CHECK-NEXT: store i8 2, i8* %ptr1, !nontemporal !0\r
+  store i8 2, i8* %ptr1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, !nontemporal !0\r
+  store volatile i8 2, i8* %ptr1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0\r
+  store i8 2, i8* %ptr1, align 1, !nontemporal !0\r
+  \r
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0\r
+  store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0\r
+  \r
+  ret void\r
+}\r
+\r
+define void @storeAtomic(){\r
+entry:\r
+  %ptr1 = alloca i8\r
+  \r
+; CHECK: store atomic i8 2, i8* %ptr1 unordered, align 1\r
+  store atomic i8 2, i8* %ptr1 unordered, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 monotonic, align 1\r
+  store atomic i8 2, i8* %ptr1 monotonic, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 release, align 1\r
+  store atomic i8 2, i8* %ptr1 release, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 seq_cst, align 1\r
+  store atomic i8 2, i8* %ptr1 seq_cst, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 unordered, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 unordered, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 monotonic, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 monotonic, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 release, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 release, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread unordered, align 1\r
+  store atomic i8 2, i8* %ptr1 singlethread unordered, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1\r
+  store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread release, align 1\r
+  store atomic i8 2, i8* %ptr1 singlethread release, align 1\r
+  \r
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1\r
+  store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1\r
+  \r
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1\r
+  store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @cmpxchg(i32* %ptr,i32 %cmp,i32 %new){\r
+entry:\r
+  ;cmpxchg [volatile] <ty>* <pointer>, <ty> <cmp>, <ty> <new> [singlethread] <ordering>\r
+\r
+; CHECK: %res1 = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic\r
+  %res1 = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic\r
+  \r
+; CHECK-NEXT: %res2 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic\r
+  %res2 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic\r
+  \r
+; CHECK-NEXT: %res3 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic\r
+  %res3 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic\r
+  \r
+; CHECK-NEXT: %res4 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic\r
+  %res4 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic\r
+  \r
+  \r
+; CHECK-NEXT: %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire\r
+  %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire\r
+  \r
+; CHECK-NEXT: %res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire\r
+  %res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire\r
+  \r
+; CHECK-NEXT: %res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire\r
+  %res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire\r
+  \r
+; CHECK-NEXT: %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire\r
+  %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire\r
+  \r
+  \r
+; CHECK-NEXT: %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release\r
+  %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release\r
+  \r
+; CHECK-NEXT: %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release\r
+  %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release\r
+  \r
+; CHECK-NEXT: %res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release\r
+  %res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release\r
+  \r
+; CHECK-NEXT: %res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release\r
+  %res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release\r
+  \r
+  \r
+; CHECK-NEXT: %res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel\r
+  %res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel\r
+  \r
+; CHECK-NEXT: %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel\r
+  %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel\r
+  \r
+; CHECK-NEXT: %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel\r
+  %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel\r
+  \r
+; CHECK-NEXT: %res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel\r
+  %res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel\r
+  \r
+  \r
+; CHECK-NEXT: %res17 = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst\r
+  %res17 = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst\r
+  \r
+; CHECK-NEXT: %res18 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst\r
+  %res18 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst\r
+  \r
+; CHECK-NEXT: %res19 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst\r
+  %res19 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst\r
+  \r
+; CHECK-NEXT: %res20 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst\r
+  %res20 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst\r
+\r
+  ret void\r
+}\r
+\r
+define void @getelementptr({i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){\r
+entry:\r
+; CHECK: %res1 = getelementptr { i8, i8 }* %s, i32 1, i32 1\r
+  %res1 = getelementptr {i8, i8}* %s, i32 1, i32 1\r
+  \r
+; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }* %s, i32 1, i32 1\r
+  %res2 = getelementptr inbounds {i8, i8}* %s, i32 1, i32 1\r
+  \r
+; CHECK-NEXT: %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets\r
+  %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets\r
+  \r
+  ret void\r
+}\r
+\r
+!0 = metadata !{ i32 1 }\r
+!1 = metadata !{}
\ No newline at end of file

diff --git a/test/Bitcode/memInstructions.3.2.ll.bc b/test/Bitcode/memInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..d75954a
Binary files /dev/null and b/test/Bitcode/memInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/miscInstructions.3.2.ll b/test/Bitcode/miscInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..bceae20
--- /dev/null
+++ b/test/Bitcode/miscInstructions.3.2.ll
@@ -0,0 +1,126 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; miscInstructions.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread miscellaneous instructions of\r
+; older bitcode files.\r
+\r
+define void @icmp(i32 %x1, i32 %x2, i32* %ptr1, i32* %ptr2, <2 x i32> %vec1, <2 x i32> %vec2){\r
+entry:\r
+; CHECK: %res1 = icmp eq i32 %x1, %x2\r
+  %res1 = icmp eq i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res2 = icmp ne i32 %x1, %x2\r
+  %res2 = icmp ne i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res3 = icmp ugt i32 %x1, %x2\r
+  %res3 = icmp ugt i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res4 = icmp uge i32 %x1, %x2\r
+  %res4 = icmp uge i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res5 = icmp ult i32 %x1, %x2\r
+  %res5 = icmp ult i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res6 = icmp ule i32 %x1, %x2\r
+  %res6 = icmp ule i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res7 = icmp sgt i32 %x1, %x2\r
+  %res7 = icmp sgt i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res8 = icmp sge i32 %x1, %x2\r
+  %res8 = icmp sge i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res9 = icmp slt i32 %x1, %x2\r
+  %res9 = icmp slt i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res10 = icmp sle i32 %x1, %x2\r
+  %res10 = icmp sle i32 %x1, %x2\r
+  \r
+; CHECK-NEXT: %res11 = icmp eq i32* %ptr1, %ptr2\r
+  %res11 = icmp eq i32* %ptr1, %ptr2\r
+  \r
+; CHECK-NEXT: %res12 = icmp eq <2 x i32> %vec1, %vec2\r
+  %res12 = icmp eq <2 x i32> %vec1, %vec2\r
+  \r
+  ret void\r
+}\r
+\r
+\r
+define void @fcmp(float %x1, float %x2, <2 x float> %vec1, <2 x float> %vec2){\r
+entry:\r
+; CHECK: %res1 = fcmp oeq float %x1, %x2\r
+  %res1 = fcmp oeq float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res2 = fcmp one float %x1, %x2\r
+  %res2 = fcmp one float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res3 = fcmp ugt float %x1, %x2\r
+  %res3 = fcmp ugt float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res4 = fcmp uge float %x1, %x2\r
+  %res4 = fcmp uge float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res5 = fcmp ult float %x1, %x2\r
+  %res5 = fcmp ult float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res6 = fcmp ule float %x1, %x2\r
+  %res6 = fcmp ule float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res7 = fcmp ogt float %x1, %x2\r
+  %res7 = fcmp ogt float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res8 = fcmp oge float %x1, %x2\r
+  %res8 = fcmp oge float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res9 = fcmp olt float %x1, %x2\r
+  %res9 = fcmp olt float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res10 = fcmp ole float %x1, %x2\r
+  %res10 = fcmp ole float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res11 = fcmp ord float %x1, %x2\r
+  %res11 = fcmp ord float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res12 = fcmp ueq float %x1, %x2\r
+  %res12 = fcmp ueq float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res13 = fcmp une float %x1, %x2\r
+  %res13 = fcmp une float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res14 = fcmp uno float %x1, %x2\r
+  %res14 = fcmp uno float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res15 = fcmp true float %x1, %x2\r
+  %res15 = fcmp true float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res16 = fcmp false float %x1, %x2\r
+  %res16 = fcmp false float %x1, %x2\r
+  \r
+; CHECK-NEXT: %res17 = fcmp oeq <2 x float> %vec1, %vec2\r
+  %res17 = fcmp oeq <2 x float> %vec1, %vec2\r
+  \r
+  ret void\r
+}\r
+\r
+declare i32 @printf(i8* noalias nocapture, ...)\r
+\r
+define void @call(i32 %x, i8* %msg ){\r
+entry:\r
+\r
+; CHECK: %res1 = call i32 @test(i32 %x)\r
+  %res1 = call i32 @test(i32 %x)\r
+  \r
+; CHECK-NEXT: %res2 = tail call i32 @test(i32 %x)\r
+  %res2 = tail call i32 @test(i32 %x)\r
+  \r
+; CHECK-NEXT: %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)\r
+  %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)\r
+  \r
+  ret void\r
+}\r
+\r
+define i32 @test(i32 %x){\r
+entry:\r
+\r
+  ret i32 %x\r
+}\r

diff --git a/test/Bitcode/miscInstructions.3.2.ll.bc b/test/Bitcode/miscInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..9d479b5
Binary files /dev/null and b/test/Bitcode/miscInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/variableArgumentIntrinsic.3.2.ll b/test/Bitcode/variableArgumentIntrinsic.3.2.ll
new file mode 100644 (file)
index 0000000..35fe0e2
--- /dev/null
+++ b/test/Bitcode/variableArgumentIntrinsic.3.2.ll
@@ -0,0 +1,33 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; vaArgIntrinsic.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread variable argument intrinsic instructions\r
+; of older bitcode files.\r
+\r
+define i32 @varArgIntrinsic(i32 %X, ...) {\r
+\r
+  %ap = alloca i8*\r
+  %ap2 = bitcast i8** %ap to i8*\r
+  \r
+; CHECK: call void @llvm.va_start(i8* %ap2)\r
+  call void @llvm.va_start(i8* %ap2)\r
+\r
+; CHECK-NEXT: %tmp = va_arg i8** %ap, i32\r
+  %tmp = va_arg i8** %ap, i32\r
+\r
+  %aq = alloca i8*\r
+  %aq2 = bitcast i8** %aq to i8*\r
+  \r
+; CHECK: call void @llvm.va_copy(i8* %aq2, i8* %ap2)\r
+  call void @llvm.va_copy(i8* %aq2, i8* %ap2)\r
+; CHECK-NEXT: call void @llvm.va_end(i8* %aq2)\r
+  call void @llvm.va_end(i8* %aq2)\r
+\r
+; CHECK-NEXT:  call void @llvm.va_end(i8* %ap2)\r
+  call void @llvm.va_end(i8* %ap2)\r
+  ret i32 %tmp\r
+}\r
+\r
+declare void @llvm.va_start(i8*)\r
+declare void @llvm.va_copy(i8*, i8*)\r
+declare void @llvm.va_end(i8*)
\ No newline at end of file

diff --git a/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc b/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc
new file mode 100644 (file)
index 0000000..066e102
Binary files /dev/null and b/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc differ