When using inline asm constraints representing

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index fc03ac55ae16883ae31f298d274050b235a0ee67..bb36d76ab753d6f462dbe10a9da404142582e8d6 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -3054,7 +3054,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
     case 'y': // Same as 'r'. Exists for compatibility.
     case 'r':
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
         return std::make_pair(0U, &Mips::CPURegsRegClass);
       assert(VT == MVT::i64 && "Unexpected type.");
       return std::make_pair(0U, &Mips::CPU64RegsRegClass);