Replace DOUT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78634 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/ExactHazardRecognizer.cpp b/lib/CodeGen/ExactHazardRecognizer.cpp
index a7fcf918a39142cad63370eb07d72812248e3370..7535caa8121485abcd17e2e9c67c07e53f32fd87 100644 (file)
--- a/lib/CodeGen/ExactHazardRecognizer.cpp
+++ b/lib/CodeGen/ExactHazardRecognizer.cpp
@@ -17,6 +17,7 @@
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"

+#include "llvm/Support/raw_ostream.h"

 #include "llvm/Target/TargetInstrItineraries.h"
 
 namespace llvm {
 #include "llvm/Target/TargetInstrItineraries.h"
 
 namespace llvm {


@@ -47,8 +48,8 @@ ExactHazardRecognizer::ExactHazardRecognizer(const InstrItineraryData &LItinData
   Scoreboard = new unsigned[ScoreboardDepth];
   ScoreboardHead = 0;
 
   Scoreboard = new unsigned[ScoreboardDepth];
   ScoreboardHead = 0;
 

-  DOUT << "Using exact hazard recognizer: ScoreboardDepth = " 
-       << ScoreboardDepth << '\n';
+  DEBUG(errs() << "Using exact hazard recognizer: ScoreboardDepth = " 
+        << ScoreboardDepth << '\n');

 }
 
 ExactHazardRecognizer::~ExactHazardRecognizer() {
 }
 
 ExactHazardRecognizer::~ExactHazardRecognizer() {


@@ -65,7 +66,7 @@ unsigned ExactHazardRecognizer::getFutureIndex(unsigned offset) {
 }
 
 void ExactHazardRecognizer::dumpScoreboard() {
 }
 
 void ExactHazardRecognizer::dumpScoreboard() {

-  DOUT << "Scoreboard:\n";
+  DEBUG(errs() << "Scoreboard:\n");

   
   unsigned last = ScoreboardDepth - 1;
   while ((last > 0) && (Scoreboard[getFutureIndex(last)] == 0))
   
   unsigned last = ScoreboardDepth - 1;
   while ((last > 0) && (Scoreboard[getFutureIndex(last)] == 0))


@@ -73,10 +74,10 @@ void ExactHazardRecognizer::dumpScoreboard() {
 
   for (unsigned i = 0; i <= last; i++) {
     unsigned FUs = Scoreboard[getFutureIndex(i)];
 
   for (unsigned i = 0; i <= last; i++) {
     unsigned FUs = Scoreboard[getFutureIndex(i)];

-    DOUT << "\t";
+    DEBUG(errs() << "\t");

     for (int j = 31; j >= 0; j--)
     for (int j = 31; j >= 0; j--)

-      DOUT << ((FUs & (1 << j)) ? '1' : '0');
-    DOUT << '\n';
+      DEBUG(errs() << ((FUs & (1 << j)) ? '1' : '0'));
+    DEBUG(errs() << '\n');

   }
 }
 
   }
 }
 


@@ -96,8 +97,8 @@ ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU
       unsigned index = getFutureIndex(cycle);
       unsigned freeUnits = IS->Units & ~Scoreboard[index];
       if (!freeUnits) {
       unsigned index = getFutureIndex(cycle);
       unsigned freeUnits = IS->Units & ~Scoreboard[index];
       if (!freeUnits) {

-        DOUT << "*** Hazard in cycle " << cycle << ", ";
-        DOUT << "SU(" << SU->NodeNum << "): ";
+        DEBUG(errs() << "*** Hazard in cycle " << cycle << ", ");
+        DEBUG(errs() << "SU(" << SU->NodeNum << "): ");

         DEBUG(SU->getInstr()->dump());
         return Hazard;
       }
         DEBUG(SU->getInstr()->dump());
         return Hazard;
       }

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 5de5e7663dac48b559d44f540bdee4f09ace27fc..4b265cc559726ae3d13bd9be3ddc675d70b57a48 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -37,6 +37,7 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"

+#include "llvm/Support/raw_ostream.h"

 #include "llvm/ADT/Statistic.h"
 #include <map>
 using namespace llvm;
 #include "llvm/ADT/Statistic.h"
 #include <map>
 using namespace llvm;


@@ -183,7 +184,7 @@ static bool isSchedulingBoundary(const MachineInstr *MI,
 }
 
 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
 }
 
 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {

-  DOUT << "PostRAScheduler\n";
+  DEBUG(errs() << "PostRAScheduler\n");

 
   const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
   const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
 
   const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
   const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();


@@ -310,7 +311,7 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
 /// Schedule - Schedule the instruction range using list scheduling.
 ///
 void SchedulePostRATDList::Schedule() {
 /// Schedule - Schedule the instruction range using list scheduling.
 ///
 void SchedulePostRATDList::Schedule() {

-  DOUT << "********** List Scheduling **********\n";
+  DEBUG(errs() << "********** List Scheduling **********\n");

   
   // Build the scheduling graph.
   BuildSchedGraph();
   
   // Build the scheduling graph.
   BuildSchedGraph();


@@ -525,8 +526,8 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
       Max = SU;
   }
 
       Max = SU;
   }
 

-  DOUT << "Critical path has total latency "
-       << (Max->getDepth() + Max->Latency) << "\n";
+  DEBUG(errs() << "Critical path has total latency "
+        << (Max->getDepth() + Max->Latency) << "\n");

 
   // Track progress along the critical path through the SUnit graph as we walk
   // the instructions.
 
   // Track progress along the critical path through the SUnit graph as we walk
   // the instructions.


@@ -691,10 +692,10 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
         if (KillIndices[NewReg] == ~0u &&
             Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
             KillIndices[AntiDepReg] <= DefIndices[NewReg]) {
         if (KillIndices[NewReg] == ~0u &&
             Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
             KillIndices[AntiDepReg] <= DefIndices[NewReg]) {

-          DOUT << "Breaking anti-dependence edge on "
-               << TRI->getName(AntiDepReg)
-               << " with " << RegRefs.count(AntiDepReg) << " references"
-               << " using " << TRI->getName(NewReg) << "!\n";
+          DEBUG(errs() << "Breaking anti-dependence edge on "
+                << TRI->getName(AntiDepReg)
+                << " with " << RegRefs.count(AntiDepReg) << " references"
+                << " using " << TRI->getName(NewReg) << "!\n");

 
           // Update the references to the old register to refer to the new
           // register.
 
           // Update the references to the old register to refer to the new
           // register.


@@ -777,7 +778,7 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
 /// count of its successors. If a successor pending count is zero, add it to
 /// the Available queue.
 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
 /// count of its successors. If a successor pending count is zero, add it to
 /// the Available queue.
 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {

-  DOUT << "*** Scheduling [" << CurCycle << "]: ";
+  DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: ");

   DEBUG(SU->dump(this));
   
   Sequence.push_back(SU);
   DEBUG(SU->dump(this));
   
   Sequence.push_back(SU);


@@ -866,7 +867,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
     } else if (!HasNoopHazards) {
       // Otherwise, we have a pipeline stall, but no other problem, just advance
       // the current cycle and try again.
     } else if (!HasNoopHazards) {
       // Otherwise, we have a pipeline stall, but no other problem, just advance
       // the current cycle and try again.

-      DOUT << "*** Advancing cycle, no work to do\n";
+      DEBUG(errs() << "*** Advancing cycle, no work to do\n");

       HazardRec->AdvanceCycle();
       ++NumStalls;
       ++CurCycle;
       HazardRec->AdvanceCycle();
       ++NumStalls;
       ++CurCycle;


@@ -874,7 +875,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
       // Otherwise, we have no instructions to issue and we have instructions
       // that will fault if we don't do this right.  This is the case for
       // processors without pipeline interlocks and other cases.
       // Otherwise, we have no instructions to issue and we have instructions
       // that will fault if we don't do this right.  This is the case for
       // processors without pipeline interlocks and other cases.

-      DOUT << "*** Emitting noop\n";
+      DEBUG(errs() << "*** Emitting noop\n");

       HazardRec->EmitNoop();
       Sequence.push_back(0);   // NULL here means noop
       ++NumNoops;
       HazardRec->EmitNoop();
       Sequence.push_back(0);   // NULL here means noop
       ++NumNoops;