Revert 67132. This is breaking some objective-c apps.

Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67701 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index a5d4caf824e15350c3b139694c6305ddf84c85b1..4bf90508e9f84bae9dd30bbde372482a6e11771f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -980,9 +980,6 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
     for (unsigned j = 0, f = NumValues; j != f; ++j) {
       MVT VT = ValueVTs[j];
 
-      unsigned NumParts = TLI.getNumRegisters(VT);
-      MVT PartVT = TLI.getRegisterType(VT);
-      SmallVector<SDValue, 4> Parts(NumParts);
       ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
 
       const Function *F = I.getParent()->getParent();
@@ -991,6 +988,19 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
       else if (F->paramHasAttr(0, Attribute::ZExt))
         ExtendKind = ISD::ZERO_EXTEND;
 
+      // FIXME: C calling convention requires the return type to be promoted to
+      // at least 32-bit. But this is not necessary for non-C calling
+      // conventions. The frontend should mark functions whose return values
+      // require promoting with signext or zeroext attributes.
+      if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
+        MVT MinVT = TLI.getRegisterType(MVT::i32);
+        if (VT.bitsLT(MinVT))
+          VT = MinVT;
+      }
+
+      unsigned NumParts = TLI.getNumRegisters(VT);
+      MVT PartVT = TLI.getRegisterType(VT);
+      SmallVector<SDValue, 4> Parts(NumParts);
       getCopyToParts(DAG, getCurDebugLoc(),
                      SDValue(RetOp.getNode(), RetOp.getResNo() + j),
                      &Parts[0], NumParts, PartVT, ExtendKind);

diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll
index cb066963b17175741bbeb4fc21de3846456ddd09..a18b6f8d05fc46566fcc20670f34375dca3fc055 100644 (file)
--- a/test/CodeGen/CellSPU/and_ops.ll
+++ b/test/CodeGen/CellSPU/and_ops.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep and    %t1.s | count 230
+; RUN: grep and    %t1.s | count 234
 ; RUN: grep andc   %t1.s | count 85
-; RUN: grep andi   %t1.s | count 35
+; RUN: grep andi   %t1.s | count 37
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 

diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll
index a578315c6b045a324de743968346090829084764..540695677205f09dc43ba920047a493d2efe9664 100644 (file)
--- a/test/CodeGen/CellSPU/eqv.ll
+++ b/test/CodeGen/CellSPU/eqv.ll
@@ -1,5 +1,8 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep eqv  %t1.s | count 18
+; RUN: grep xshw %t1.s | count 6
+; RUN: grep xsbh %t1.s | count 3
+; RUN: grep andi %t1.s | count 3
 
 ; Test the 'eqv' instruction, whose boolean expression is:
 ; (a & b) | (~a & ~b), which simplifies to

diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll
index ccbd5d90e54ae1f65c9f3698be36cc70c810aba4..841a3ec54d6f23085a21e36bbfde093c77ea9e1f 100644 (file)
--- a/test/CodeGen/CellSPU/nand.ll
+++ b/test/CodeGen/CellSPU/nand.ll
@@ -1,6 +1,8 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep nand   %t1.s | count 90
-; RUN: grep and    %t1.s | count 90
+; RUN: grep and    %t1.s | count 94
+; RUN: grep xsbh   %t1.s | count 2
+; RUN: grep xshw   %t1.s | count 4
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll
index 49e5ec36d28814a643e9361d6f68c583926b429c..4e9da8f1297224faee3919001f06d6f771ec218f 100644 (file)
--- a/test/CodeGen/CellSPU/or_ops.ll
+++ b/test/CodeGen/CellSPU/or_ops.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep and    %t1.s | count 2
 ; RUN: grep orc    %t1.s | count 85
 ; RUN: grep ori    %t1.s | count 30
 ; RUN: grep orhi   %t1.s | count 30

diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 3b7dacd3cd762e3bef2aef22074d333c502b0918..3c26baa7c7ab705d5a0db162a6ca5010f369e0b1 100644 (file)
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -3,6 +3,8 @@
 ; RUN: grep {shlhi     }  %t1.s | count 3
 ; RUN: grep {shl       }  %t1.s | count 9
 ; RUN: grep {shli      }  %t1.s | count 3
+; RUN: grep {xshw      }  %t1.s | count 5
+; RUN: grep {and       }  %t1.s | count 5
 ; RUN: grep {andi      }  %t1.s | count 2
 ; RUN: grep {rotmi     }  %t1.s | count 2
 ; RUN: grep {rotqmbyi  }  %t1.s | count 1

diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
index f59bfd49acf2d4ba6a8d180c5edb584ddc83fcaf..f2f35ef4dbc45d565eb81fd7434fe63ea1c07eea 100644 (file)
--- a/test/CodeGen/CellSPU/stores.ll
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -6,13 +6,13 @@
 ; RUN: grep 771                 %t1.s | count 4
 ; RUN: grep 515                 %t1.s | count 2
 ; RUN: grep 1799                %t1.s | count 2
-; RUN: grep 1543                %t1.s | count 3
-; RUN: grep 1029                %t1.s | count 1
+; RUN: grep 1543                %t1.s | count 5
+; RUN: grep 1029                %t1.s | count 3
 ; RUN: grep {shli.*, 4}         %t1.s | count 4
 ; RUN: grep stqx                %t1.s | count 4
-; RUN: grep ilhu                %t1.s | count 9
-; RUN: grep iohl                %t1.s | count 6
-; RUN: grep shufb               %t1.s | count 13
+; RUN: grep ilhu                %t1.s | count 11
+; RUN: grep iohl                %t1.s | count 8
+; RUN: grep shufb               %t1.s | count 15
 ; RUN: grep frds                %t1.s | count 1
 
 ; ModuleID = 'stores.bc'

diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
index 260a7f41989940858e2028b6a611d78512364d77..82d319dd1050b859f031d25bf1808c97d5d86867 100644 (file)
--- a/test/CodeGen/CellSPU/struct_1.ll
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -3,6 +3,8 @@
 ; RUN: grep lqa     %t1.s | count 5
 ; RUN: grep lqd     %t1.s | count 11
 ; RUN: grep rotqbyi %t1.s | count 7
+; RUN: grep xshw    %t1.s | count 1
+; RUN: grep andi    %t1.s | count 5
 ; RUN: grep cbd     %t1.s | count 3
 ; RUN: grep chd     %t1.s | count 1
 ; RUN: grep cwd     %t1.s | count 3
@@ -12,6 +14,8 @@
 ; RUN: grep ilhu    %t2.s | count 16
 ; RUN: grep lqd     %t2.s | count 16
 ; RUN: grep rotqbyi %t2.s | count 7
+; RUN: grep xshw    %t2.s | count 1
+; RUN: grep andi    %t2.s | count 5
 ; RUN: grep cbd     %t2.s | count 3
 ; RUN: grep chd     %t2.s | count 1
 ; RUN: grep cwd     %t2.s | count 3

diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
index ffb1e83a276d35a1c6b08087b32dafea576d99cc..b62d2c61bba7af9d0089e296a7bb9def9fa729a2 100644 (file)
--- a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
+++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep {movsbl}
+; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl}
 
 @X = global i32 0               ; <i32*> [#uses=1]
 

diff --git a/test/CodeGen/X86/20090313-signext.ll b/test/CodeGen/X86/20090313-signext.ll
index b6c9ecbf47a4057a5022e26da76705db2459cb85..7313670a1c33146c4e8c39f98d893f03d185bdbc 100644 (file)
--- a/test/CodeGen/X86/20090313-signext.ll
+++ b/test/CodeGen/X86/20090313-signext.ll
@@ -1,6 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=pic > %t
 ; RUN: grep {movswl    %ax, %edi} %t
 ; RUN: grep {movw      (%rax), %ax} %t
+; XFAIL: *
 
 @x = common global i16 0
 

diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll
index 8cdf4ac22d92a7f54260af8bad7b14875922b0b2..6e3156beb0f61409702bbaa7bd8d7883046753c6 100644 (file)
--- a/test/CodeGen/X86/const-select.ll
+++ b/test/CodeGen/X86/const-select.ll
@@ -10,7 +10,7 @@ entry:
        ret float %iftmp.0.0
 }
 
-; RUN: llvm-as < %s | llc | grep {movb.*(%e.x,%e.x,4), %al}
+; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax}
 define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
 entry:
        %0 = fcmp olt double %F, 4.200000e+01           ; <i1> [#uses=1]

diff --git a/test/CodeGen/X86/sext-trunc.ll b/test/CodeGen/X86/sext-trunc.ll
index df401564c24f91e28673bb0f1acb2a016c2b631c..97b46668270239563417daa14070f566b2cc5104 100644 (file)
--- a/test/CodeGen/X86/sext-trunc.ll
+++ b/test/CodeGen/X86/sext-trunc.ll
@@ -1,6 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 > %t
-; RUN: grep movb %t
-; RUN: not grep movsbl %t
+; RUN: grep movsbl %t
 ; RUN: not grep movz %t
 ; RUN: not grep and %t
 

diff --git a/test/CodeGen/X86/split-eh-lpad-edges.ll b/test/CodeGen/X86/split-eh-lpad-edges.ll
index 7808ad63168d4864d046515a8437e75574c4dc19..281ee7782da1e215cd32a4552c3cd81a749b2d3b 100644 (file)
--- a/test/CodeGen/X86/split-eh-lpad-edges.ll
+++ b/test/CodeGen/X86/split-eh-lpad-edges.ll
@@ -32,38 +32,3 @@ lpad:                ; preds = %invcont26, %invcont, %entry
 }
 
 declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep jmp
-; rdar://6647639
-; XFAIL: *
-
-       %struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags }
-       %struct.NSArray = type { %struct.NSObject }
-       %struct.NSAutoreleasePool = type { %struct.NSObject, i8*, i8*, i8*, i8* }
-       %struct.NSObject = type { %struct.NSObject* }
-       %struct.__attributeDescriptionFlags = type <{ i32 }>
-       %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
-       %struct.objc_selector = type opaque
-@"\01l_objc_msgSend_fixup_alloc" = external global %struct._message_ref_t, align 16            ; <%struct._message_ref_t*> [#uses=2]
-
-define %struct.NSArray* @newFetchedRowsForFetchPlan_MT(%struct.FetchPlanHeader* %fetchPlan, %struct.objc_selector* %selectionMethod, %struct.NSObject* %selectionParameter) ssp {
-entry:
-       %0 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
-                       to label %invcont unwind label %lpad            ; <%struct.NSObject*> [#uses=1]
-
-invcont:               ; preds = %entry
-       %1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
-                       to label %invcont26 unwind label %lpad          ; <%struct.NSObject*> [#uses=0]
-
-invcont26:             ; preds = %invcont
-       %2 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
-                       to label %invcont27 unwind label %lpad          ; <%struct.NSObject*> [#uses=0]
-
-invcont27:             ; preds = %invcont26
-       unreachable
-
-lpad:          ; preds = %invcont26, %invcont, %entry
-       %pool.1 = phi %struct.NSAutoreleasePool* [ null, %entry ], [ null, %invcont ], [ null, %invcont26 ]             ; <%struct.NSAutoreleasePool*> [#uses=0]
-       unreachable
-}
-
-declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)