// t_addrmode_is2 := reg + imm5 * 2
//
+def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
def t_addrmode_is2 : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
let EncoderMethod = "getAddrModeISOpValue";
let DecoderMethod = "DecodeThumbAddrModeIS";
let PrintMethod = "printThumbAddrModeImm5S2Operand";
+ let ParserMatchClass = t_addrmode_is2_asm_operand;
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
}
int64_t Val = Mem.OffsetImm->getValue();
return Val >= 0 && Val <= 124 && (Val % 4) == 0;
}
+ bool isMemThumbRIs2() const {
+ if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+ !isARMLowRegister(Mem.BaseRegNum))
+ return false;
+ // Immediate offset, multiple of 4 in range [0, 62].
+ if (!Mem.OffsetImm) return true;
+ int64_t Val = Mem.OffsetImm->getValue();
+ return Val >= 0 && Val <= 62 && (Val % 2) == 0;
+ }
bool isMemThumbRIs1() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 ||
!isARMLowRegister(Mem.BaseRegNum))
Inst.addOperand(MCOperand::CreateImm(Val));
}
+ void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 2 && "Invalid number of operands!");
+ int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
+ Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+ Inst.addOperand(MCOperand::CreateImm(Val));
+ }
+
void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
ldrb r6, [r4, r5]
@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d]
+
+
+@------------------------------------------------------------------------------
+@ LDRH (immediate)
+@------------------------------------------------------------------------------
+ ldrh r3, [r3]
+ ldrh r4, [r6, #2]
+ ldrh r5, [r7, #62]
+
+@ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88]
+@ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88]
+@ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f]
+
+
+@------------------------------------------------------------------------------
+@ LDRH (register)
+@------------------------------------------------------------------------------
+ ldrh r6, [r2, r6]
+
+@ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b]