make UpdateValueMap handle the possiblity that we could be

copying into the right register, avoiding a copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68889 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 7e300536748df60c1647e5ca7f5e7f57a66a34f8..251e96a771c9792c7418c14c4351281363f8e5c8 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -158,7 +158,7 @@ unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
   unsigned &AssignedReg = ValueMap[I];
   if (AssignedReg == 0)
     AssignedReg = Reg;
-  else {
+  else if (Reg != AssignedReg) {
     const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
     TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
                      Reg, RegClass, RegClass);