Fix 80-columns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139525 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 25ee19158cc7a3a2f227945779bb5a1a1b2212db..f20b23f55297514bc3349710031473b5d6440787 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1999,21 +1999,25 @@ let neverHasSideEffects = 1 in {
 
 let Constraints = "$src1 = $dst" in {
 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
-                  (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
-                  "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
-                  [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
+              (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
+              "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
+              [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2,
+                                         imm:$cc))]>, XS;
 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
-                  (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
-                  "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
-                  [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
+              (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
+              "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
+              [(set FR32:$dst, (X86cmpss (f32 FR32:$src1),
+                                         (loadf32 addr:$src2), imm:$cc))]>, XS;
 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
-                  (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
-                  "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
-                  [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
+              (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
+              "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
+              [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2,
+                                         imm:$cc))]>, XD;
 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
-                  (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
-                  "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
-                  [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
+              (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
+              "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
+              [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2),
+                                         imm:$cc))]>, XD;
 }
 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,