Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45699 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 42e41279f60774cc7df7f3edcf8456d4aec52698..a24140cb0d5c785dbc7a02f677c1ac8500810be4 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -771,19 +771,15 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
   switch (MI->getOpcode()) {
   default: break;
   case X86::MOV32rm:
-    if (MI->getOperand(1).isRegister()) {
-      unsigned Reg = MI->getOperand(1).getReg();
-      const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>();
-
-      // Loads from stubs of global addresses are side effect free.
-      if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
-          MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
-          MI->getOperand(4).isGlobal() &&
-          ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, false) &&
-          MI->getOperand(2).getImm() == 1 &&
-          MI->getOperand(3).getReg() == 0)
-        return true;
-    }
+    // Loads from stubs of global addresses are side effect free.
+    if (MI->getOperand(1).isReg() &&
+        MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
+        MI->getOperand(4).isGlobal() &&
+        TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad
+          (MI->getOperand(4).getGlobal(), TM, false) &&
+        MI->getOperand(2).getImm() == 1 &&
+        MI->getOperand(3).getReg() == 0)
+      return true;
     // FALLTHROUGH
   case X86::MOV8rm:
   case X86::MOV16rm: