[TableGen] Allow shift operators to take bits<n>

Convert the operand to int if possible, i.e. if the value is properly
initialized.  (I suppose there is further room for improvement here to also
peform the shift if the uninitialized bits are shifted out.)

With this little change we can now compute the scaling factor for compressed
displacement with pure tablegen code in the X86 backend.  This is useful
because both the X86-disassembler-specific part of tablegen and the assembler
need this and TD is the natural sharing place.

The patch also adds the missing documentation for the shift and add operator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213277 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/TableGen/LangIntro.rst b/docs/TableGen/LangIntro.rst
index 3e74dffb00e23a63bbd67a7e3c99d70247410333..0f8b3f6213640feccbff1e311d1290038edbdfc1 100644 (file)
--- a/docs/TableGen/LangIntro.rst
+++ b/docs/TableGen/LangIntro.rst
@@ -208,6 +208,12 @@ supported include:
     on string, int and bit objects.  Use !cast<string> to compare other types of
     objects.
 
     on string, int and bit objects.  Use !cast<string> to compare other types of
     objects.
 

+``!shl(a,b)``
+``!srl(a,b)``
+``!sra(a,b)``
+``!add(a,b)``
+    The usual logical and arithmetic operators.
+

 Note that all of the values have rules specifying how they convert to values
 for different types.  These rules allow you to assign a value like "``7``"
 to a "``bits<4>``" value, for example.
 Note that all of the values have rules specifying how they convert to values
 for different types.  These rules allow you to assign a value like "``7``"
 to a "``bits<4>``" value, for example.

diff --git a/lib/TableGen/Record.cpp b/lib/TableGen/Record.cpp
index f7843dc8360bd1e1e1cc495a2ece8b03f95c6d01..0f40904ae91951b824a1528d7bd4a3ba3440fcfe 100644 (file)
--- a/lib/TableGen/Record.cpp
+++ b/lib/TableGen/Record.cpp
@@ -955,8 +955,10 @@ Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const {
   case SHL:
   case SRA:
   case SRL: {
   case SHL:
   case SRA:
   case SRL: {

-    IntInit *LHSi = dyn_cast<IntInit>(LHS);
-    IntInit *RHSi = dyn_cast<IntInit>(RHS);
+    IntInit *LHSi =
+      dyn_cast_or_null<IntInit>(LHS->convertInitializerTo(IntRecTy::get()));
+    IntInit *RHSi =
+      dyn_cast_or_null<IntInit>(RHS->convertInitializerTo(IntRecTy::get()));

     if (LHSi && RHSi) {
       int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
       int64_t Result;
     if (LHSi && RHSi) {
       int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
       int64_t Result;

diff --git a/test/TableGen/math.td b/test/TableGen/math.td
index 59d16ae908e2948ea6c10cffcd10752846c58530..71c60579de21ba513aac313b9216dcb787d58731 100644 (file)
--- a/test/TableGen/math.td
+++ b/test/TableGen/math.td
@@ -1,6 +1,16 @@
 // RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
 
 // RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
 

+def shifts {
+    bits<2> b = 0b10;
+    int i = 2;
+    int shifted_b = !shl(b, 2);
+    int shifted_i = !shl(i, 2);
+}
+// CHECK: def shifts
+// CHECK: shifted_b = 8
+// CHECK: shifted_i = 8
+

 class Int<int value> {
   int Value = value;
 }
 class Int<int value> {
   int Value = value;
 }