Only one instruction pair needed changing: SMULH & UMULH. The previous
code worked, but MC was doing extra work treating Ra as a valid
operand (which then got completely overwritten in MCCodeEmitter).
No behaviour change, so no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203772
91177308-0d34-0410-b5e6-
96231b3b80d8
include "AArch64InstrInfo.td"
-def AArch64InstrInfo : InstrInfo;
+def AArch64InstrInfo : InstrInfo {
+ let noNamedPositionallyEncodedOperands = 1;
+}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
dag outs, dag ins, string asmstr,
list<dag> patterns, InstrItinClass itin>
: A64InstRdnm<outs, ins, asmstr, patterns, itin> {
- bits<5> Ra;
-
let Inst{31} = sf;
let Inst{30-29} = opcode{5-4};
let Inst{28-24} = 0b11011;
let Inst{23-21} = opcode{3-1};
// Inherits Rm in 20-16
let Inst{15} = opcode{0};
- let Inst{14-10} = Ra;
+ // {14-10} mostly Ra, but unspecified for SMULH/UMULH
// Inherits Rn in 9-5
// Inherits Rd in 4-0
}
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
[(set AccTy:$Rd, pattern)], NoItinerary>,
Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
+ bits<5> Ra;
+ let Inst{14-10} = Ra;
+
RegisterClass AccGPR = AccReg;
RegisterClass SrcGPR = SrcReg;
}