Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 557b1a3bb60a07a8d2005ebe6d0d8e1b0980eb5a..0cf822aa0e85104c979de514fbde282b14aeb474 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -61,7 +61,7 @@ public:
   };
 
   enum MachineOperandType {
-    MO_VirtualRegister,         // virtual register for *value
+    MO_Register,                // Register operand.
     MO_Immediate,               // Immediate Operand
     MO_MachineBasicBlock,       // MachineBasicBlock reference
     MO_FrameIndex,              // Abstract Stack Frame Index
@@ -93,12 +93,17 @@ private:
     extra.offset = 0;
   }
 
-  MachineOperand(int64_t ImmVal, MachineOperandType OpTy, int Offset = 0)
-    : flags(0), opType(OpTy) {
+  MachineOperand(int64_t ImmVal) : flags(0), opType(MO_Immediate) {
     contents.immedVal = ImmVal;
-    extra.offset = Offset;
+    extra.offset = 0;
   }
 
+  MachineOperand(unsigned Idx, MachineOperandType OpTy)
+    : flags(0), opType(OpTy) {
+    contents.immedVal = Idx;
+    extra.offset = 0;
+  }
+  
   MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
     : flags(UseTy), opType(OpTy) {
     zeroContents();
@@ -152,7 +157,7 @@ public:
 
   /// Accessors that tell you what kind of MachineOperand you're looking at.
   ///
-  bool isRegister() const { return opType == MO_VirtualRegister; }
+  bool isRegister() const { return opType == MO_Register; }
   bool isImmediate() const { return opType == MO_Immediate; }
   bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
   bool isFrameIndex() const { return opType == MO_FrameIndex; }
@@ -245,7 +250,7 @@ public:
   /// the specified value.  If an operand is known to be an register already,
   /// the setReg method should be used.
   void ChangeToRegister(unsigned Reg) {
-    opType = MO_VirtualRegister;
+    opType = MO_Register;
     extra.regNum = Reg;
   }
 
@@ -353,16 +358,6 @@ public:
   // Accessors to add operands when building up machine instructions
   //
 
-  /// addRegOperand - Add a symbolic virtual register reference...
-  ///
-  void addRegOperand(int reg, bool isDef) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(
-      MachineOperand(reg, MachineOperand::MO_VirtualRegister,
-                     isDef ? MachineOperand::Def : MachineOperand::Use));
-  }
-
   /// addRegOperand - Add a symbolic virtual register reference...
   ///
   void addRegOperand(int reg,
@@ -370,26 +365,16 @@ public:
     assert(!OperandsComplete() &&
            "Trying to add an operand to a machine instr that is already done!");
     operands.push_back(
-      MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
+      MachineOperand(reg, MachineOperand::MO_Register, UTy));
   }
 
-  /// addZeroExtImmOperand - Add a zero extended constant argument to the
+  /// addImmOperand - Add a zero extended constant argument to the
   /// machine instruction.
   ///
-  void addZeroExtImmOperand(int intValue) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(
-      MachineOperand(intValue, MachineOperand::MO_Immediate));
-  }
-
-  /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument
-  /// to the machine instruction.
-  ///
-  void addZeroExtImm64Operand(uint64_t intValue) {
+  void addImmOperand(int64_t Val) {
     assert(!OperandsComplete() &&
            "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate));
+    operands.push_back(MachineOperand(Val));
   }
 
   void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {

diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 3a25ea2f113dec5bfc033ea2c17fc8b9d0966d15..36ee998cbcb662dc2a3059528fb32a0b2e6be14d 100644 (file)
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -42,22 +42,22 @@ public:
 
   /// addImm - Add a new immediate operand.
   ///
-  const MachineInstrBuilder &addImm(int Val) const {
-    MI->addZeroExtImmOperand(Val);
+  const MachineInstrBuilder &addImm(int64_t Val) const {
+    MI->addImmOperand(Val);
     return *this;
   }
 
   /// addZImm - Add a new zero extended immediate operand...
   ///
   const MachineInstrBuilder &addZImm(unsigned Val) const {
-    MI->addZeroExtImmOperand(Val);
+    MI->addImmOperand(Val);
     return *this;
   }
 
   /// addImm64 - Add a new 64-bit immediate operand...
   ///
   const MachineInstrBuilder &addImm64(uint64_t Val) const {
-    MI->addZeroExtImm64Operand(Val);
+    MI->addImmOperand(Val);
     return *this;
   }
 

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index b1fb52a13a5df1ff24c845ec724612ea9982a58e..f2a604cf6d0af9a0406f2ad39b186bd29b0c18fc 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -138,7 +138,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
   if (TM) MRI = TM->getRegisterInfo();
 
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     OutputReg(OS, MO.getReg(), MRI);
     break;
   case MachineOperand::MO_Immediate:
@@ -235,7 +235,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
 
 std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     OutputReg(OS, MO.getReg());
     break;
   case MachineOperand::MO_Immediate:

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 2b7b877cb174aeea692ca1257be945d02542feb6..cf1227964a591697bc08721ec2d439a2fb808c0c 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -104,7 +104,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     }
   } else if (ConstantSDNode *C =
              dyn_cast<ConstantSDNode>(Op)) {
-    MI->addZeroExtImm64Operand(C->getValue());
+    MI->addImmOperand(C->getValue());
   } else if (RegisterSDNode*R =
              dyn_cast<RegisterSDNode>(Op)) {
     MI->addRegOperand(R->getReg(), MachineOperand::Use);
@@ -303,7 +303,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
         unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
         unsigned NumVals = Flags >> 3;
         
-        MI->addZeroExtImm64Operand(Flags);
+        MI->addImmOperand(Flags);
         ++i;  // Skip the ID value.
         
         switch (Flags & 7) {
@@ -323,7 +323,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
         case 3: { // Immediate.
           assert(NumVals == 1 && "Unknown immediate value!");
           uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
-          MI->addZeroExtImm64Operand(Val);
+          MI->addImmOperand(Val);
           ++i;
           break;
         }

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index e51b78457bb886c3ecdab54ddb9e5fff481d956e..59a850537677b5ea32ab7196509c2be63e1b6aa1 100644 (file)
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
 void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
 {
   const MachineOperand &MO = MI->getOperand(opNum);
-  if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+  if (MO.getType() == MachineOperand::MO_Register) {
     assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
     O << TM.getRegisterInfo()->get(MO.getReg()).Name;
   } else if (MO.isImmediate()) {
@@ -93,7 +93,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
   int new_symbol;
 
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     O << RI.get(MO.getReg()).Name;
     return;
 

diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 86b8432a3f40f502093f5f3f6a63c60e12bbae8e..13c2dfbec52e3d08e503dd4ca62a44c2e06e79fa 100644 (file)
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -66,7 +66,7 @@ namespace {
     // This method is used by the tablegen'erated instruction printer.
     void printOperand(const MachineInstr *MI, unsigned OpNo){
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+      if (MO.getType() == MachineOperand::MO_Register) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
         //XXX Bug Workaround: See note in Printer::doInitialization about %.
         O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@@ -173,7 +173,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
                              bool isBRCALLinsn /* = false */) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     O << RI.get(MO.getReg()).Name;
     return;
 

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 5e30fe073cb61c9335b462b59c18fcf632c1bf6e..dbd3b03e7bcc2afba0f4807cbf11a95e96d17a8c 100644 (file)
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,7 +86,7 @@ namespace {
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+      if (MO.isRegister()) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
         O << TM.getRegisterInfo()->get(MO.getReg()).Name;
       } else if (MO.isImmediate()) {

diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index d95ca9c1f9700284a7c1a325efab691f662a170f..47ed6fcda783351611bdb4751273a1e1d9593b22 100644 (file)
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -146,7 +146,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
     CloseParen = true;
   }
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
     else
@@ -188,16 +188,16 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
   
   MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
   
-  if (OpTy == MachineOperand::MO_VirtualRegister &&
+  if (MI->getOperand(opNum+1).isRegister() &&
       MI->getOperand(opNum+1).getReg() == SP::G0)
     return;   // don't print "+%g0"
-  if (OpTy == MachineOperand::MO_Immediate &&
+  if (MI->getOperand(opNum+1).isImmediate() &&
       MI->getOperand(opNum+1).getImmedValue() == 0)
     return;   // don't print "+0"
   
   O << "+";
-  if (OpTy == MachineOperand::MO_GlobalAddress ||
-      OpTy == MachineOperand::MO_ConstantPoolIndex) {
+  if (MI->getOperand(opNum+1).isGlobalAddress() ||
+      MI->getOperand(opNum+1).isConstantPoolIndex()) {
     O << "%lo(";
     printOperand(MI, opNum+1);
     O << ")";

diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index 122b012453ddef455843aa736279b66728928dda..92e22945b7ac6300517c33e04701ffbfbe2e1c34 100755 (executable)
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -108,7 +108,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   const MachineOperand &MO = MI->getOperand(OpNo);
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            "Virtual registers should not make it this far!");
     O << '%';

diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index 07dab8a478c874b25e670622bdecb3ede5d8daf8..af58df1e956007ce3bf8be4116705058d03d671b 100755 (executable)
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -100,7 +100,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
                                  const char *Modifier) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
+  case MachineOperand::MO_Register:
     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << RI.get(MO.getReg()).Name;
     else

diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index 28ccfc9ed0948622da3d107e7d0093c8ff616eb8..c594e462551cc2b91f883e567cbf8169786d9ef5 100755 (executable)
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -37,7 +37,7 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
   void printOperand(const MachineInstr *MI, unsigned OpNo,
                     const char *Modifier = 0) {
     const MachineOperand &MO = MI->getOperand(OpNo);
-    if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+    if (MO.isRegister()) {
       assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
       O << TM.getRegisterInfo()->get(MO.getReg()).Name;
     } else {