Ensure bitcode encoding of instructions and their operands stays stable.

This includes instructions with aggregate operands (insert/extract), instructions with vector operands (insert/extract/shuffle), binary arithmetic and bitwise instructions, conversion instructions and terminators.

Work was done by lama.saba@intel.com.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202262 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Bitcode/aggregateInstructions.3.2.ll b/test/Bitcode/aggregateInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..9352390
--- /dev/null
+++ b/test/Bitcode/aggregateInstructions.3.2.ll
@@ -0,0 +1,33 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread instructions with aggregate operands\r
+; in older bitcode files.\r
+\r
+define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){\r
+entry:\r
+; CHECK: %res1 = extractvalue [4 x i8] %x1, 0\r
+  %res1 = extractvalue [4 x i8] %x1, 0\r
+  \r
+; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1\r
+  %res2 = extractvalue [4 x [4 x i8 ]] %x2, 1\r
+\r
+; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1\r
+  %res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1\r
+  \r
+; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1\r
+  %res4 = extractvalue {{i32, float}} %x3, 0, 1\r
+\r
+  ret void\r
+}\r
+\r
+define void @insertvalue([4 x [4 x i8 ]] %x1){\r
+entry:\r
+; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0\r
+  %res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0\r
+  \r
+; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0\r
+  %res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0\r
+\r
+  ret void\r
+}
\ No newline at end of file

diff --git a/test/Bitcode/aggregateInstructions.3.2.ll.bc b/test/Bitcode/aggregateInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..053f85f
Binary files /dev/null and b/test/Bitcode/aggregateInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll b/test/Bitcode/binaryFloatInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..f94d82d
--- /dev/null
+++ b/test/Bitcode/binaryFloatInstructions.3.2.ll
@@ -0,0 +1,120 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread binary float instructions from\r
+; older bitcode files.\r
+\r
+define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){\r
+entry:\r
+; CHECK: %res1 = fadd float %x1, %x1\r
+  %res1 = fadd float %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd double %x2, %x2\r
+  %res2 = fadd double %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd half %x3, %x3\r
+  %res3 = fadd half %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4\r
+  %res4 = fadd fp128 %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5\r
+  %res5 = fadd x86_fp80 %x5, %x5\r
+  \r
+; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6\r
+  %res6 = fadd ppc_fp128 %x6, %x6\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x float> %x1, %x1\r
+  %res1 = fadd <2 x float> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2\r
+  %res2 = fadd <3 x float> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3\r
+  %res3 = fadd <4 x float> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4\r
+  %res4 = fadd <8 x float> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5\r
+  %res5 = fadd <16 x float> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x double> %x1, %x1\r
+  %res1 = fadd <2 x double> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2\r
+  %res2 = fadd <3 x double> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3\r
+  %res3 = fadd <4 x double> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4\r
+  %res4 = fadd <8 x double> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5\r
+  %res5 = fadd <16 x double> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x half> %x1, %x1\r
+  %res1 = fadd <2 x half> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2\r
+  %res2 = fadd <3 x half> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3\r
+  %res3 = fadd <4 x half> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4\r
+  %res4 = fadd <8 x half> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5\r
+  %res5 = fadd <16 x half> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fsub(float %x1){\r
+entry:\r
+; CHECK: %res1 = fsub float %x1, %x1\r
+  %res1 = fsub float %x1, %x1\r
+\r
+  ret void\r
+}\r
+\r
+define void @fmul(float %x1){\r
+entry:\r
+; CHECK: %res1 = fmul float %x1, %x1\r
+  %res1 = fmul float %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fdiv(float %x1){\r
+entry:\r
+; CHECK: %res1 = fdiv float %x1, %x1\r
+  %res1 = fdiv float %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @frem(float %x1){\r
+entry:\r
+; CHECK: %res1 = frem float %x1, %x1\r
+  %res1 = frem float %x1, %x1\r
+\r
+  ret void\r
+}\r

diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll.bc b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..8dbb4e4
Binary files /dev/null and b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll b/test/Bitcode/binaryIntInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..b08501c
--- /dev/null
+++ b/test/Bitcode/binaryIntInstructions.3.2.ll
@@ -0,0 +1,177 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread binary integer instructions from\r
+; older bitcode files.\r
+\r
+define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){\r
+entry:\r
+; CHECK: %res1 = add i1 %x1, %x1\r
+  %res1 = add i1 %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = add i8 %x2, %x2\r
+  %res2 = add i8 %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = add i16 %x3, %x3\r
+  %res3 = add i16 %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = add i32 %x4, %x4\r
+  %res4 = add i32 %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = add i64 %x5, %x5\r
+  %res5 = add i64 %x5, %x5\r
+  \r
+; CHECK: %res6 = add nuw i1 %x1, %x1\r
+  %res6 = add nuw i1 %x1, %x1\r
+  \r
+; CHECK: %res7 = add nsw i1 %x1, %x1\r
+  %res7 = add nsw i1 %x1, %x1\r
+  \r
+; CHECK: %res8 = add nuw nsw i1 %x1, %x1\r
+  %res8 = add nuw nsw i1 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){\r
+entry:\r
+; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1\r
+  %res1 = add nuw nsw <2 x i8> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2\r
+  %res2 = add nuw nsw <3 x i8> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3\r
+  %res3 = add nuw nsw <4 x i8> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4\r
+  %res4 = add nuw nsw <8 x i8> %x4, %x4\r
+  \r
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5\r
+  %res5 = add nuw nsw <16 x i8> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){\r
+entry:\r
+; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1\r
+  %res1 = add nuw nsw <2 x i16> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2\r
+  %res2 = add nuw nsw <3 x i16> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3\r
+  %res3 = add nuw nsw <4 x i16> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4\r
+  %res4 = add nuw nsw <8 x i16> %x4, %x4\r
+  \r
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5\r
+  %res5 = add nuw nsw <16 x i16> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){\r
+entry:\r
+; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1\r
+  %res1 = add nuw nsw <2 x i32> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2\r
+  %res2 = add nuw nsw <3 x i32> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3\r
+  %res3 = add nuw nsw <4 x i32> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4\r
+  %res4 = add nuw nsw <8 x i32> %x4, %x4\r
+  \r
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5\r
+  %res5 = add nuw nsw <16 x i32> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){\r
+entry:\r
+; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1\r
+  %res1 = add nuw nsw <2 x i64> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2\r
+  %res2 = add nuw nsw <3 x i64> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3\r
+  %res3 = add nuw nsw <4 x i64> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4\r
+  %res4 = add nuw nsw <8 x i64> %x4, %x4\r
+  \r
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5\r
+  %res5 = add nuw nsw <16 x i64> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @sub(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = sub i8 %x1, %x1\r
+  %res1 = sub i8 %x1, %x1\r
+  \r
+; CHECK: %res2 = sub nuw i8 %x1, %x1\r
+  %res2 = sub nuw i8 %x1, %x1\r
+  \r
+; CHECK: %res3 = sub nsw i8 %x1, %x1\r
+  %res3 = sub nsw i8 %x1, %x1\r
+  \r
+; CHECK: %res4 = sub nuw nsw i8 %x1, %x1\r
+  %res4 = sub nuw nsw i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @mul(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = mul i8 %x1, %x1\r
+  %res1 = mul i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @udiv(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = udiv i8 %x1, %x1\r
+  %res1 = udiv i8 %x1, %x1\r
+  \r
+; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1\r
+  %res2 = udiv exact i8 %x1, %x1\r
+\r
+  ret void\r
+}\r
+\r
+define void @sdiv(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = sdiv i8 %x1, %x1\r
+  %res1 = sdiv i8 %x1, %x1\r
+  \r
+; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1\r
+  %res2 = sdiv exact i8 %x1, %x1\r
+\r
+  ret void\r
+}\r
+\r
+define void @urem(i32 %x1){\r
+entry:\r
+; CHECK: %res1 = urem i32 %x1, %x1\r
+  %res1 = urem i32 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @srem(i32 %x1){\r
+entry:\r
+; CHECK: %res1 = srem i32 %x1, %x1\r
+  %res1 = srem i32 %x1, %x1\r
+  \r
+  ret void\r
+}\r

diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll.bc b/test/Bitcode/binaryIntInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..749e0c3
Binary files /dev/null and b/test/Bitcode/binaryIntInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll b/test/Bitcode/bitwiseInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..6225a08
--- /dev/null
+++ b/test/Bitcode/bitwiseInstructions.3.2.ll
@@ -0,0 +1,68 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread bitwise instructions from\r
+; older bitcode files.\r
+\r
+define void @shl(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = shl i8 %x1, %x1\r
+  %res1 = shl i8 %x1, %x1\r
+  \r
+; CHECK: %res2 = shl nuw i8 %x1, %x1\r
+  %res2 = shl nuw i8 %x1, %x1\r
+  \r
+; CHECK: %res3 = shl nsw i8 %x1, %x1\r
+  %res3 = shl nsw i8 %x1, %x1\r
+\r
+; CHECK: %res4 = shl nuw nsw i8 %x1, %x1\r
+  %res4 = shl nuw nsw i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @lshr(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = lshr i8 %x1, %x1\r
+  %res1 = lshr i8 %x1, %x1\r
+  \r
+; CHECK: %res2 = lshr exact i8 %x1, %x1\r
+  %res2 = lshr exact i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @ashr(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = ashr i8 %x1, %x1\r
+  %res1 = ashr i8 %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1\r
+  %res2 = ashr exact i8 %x1, %x1\r
+\r
+  ret void\r
+}\r
+\r
+define void @and(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = and i8 %x1, %x1\r
+  %res1 = and i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @or(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = or i8 %x1, %x1\r
+  %res1 = or i8 %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @xor(i8 %x1){\r
+entry:\r
+; CHECK: %res1 = xor i8 %x1, %x1\r
+  %res1 = xor i8 %x1, %x1\r
+  \r
+  ret void\r
+}
\ No newline at end of file

diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll.bc b/test/Bitcode/bitwiseInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..136a7c9
Binary files /dev/null and b/test/Bitcode/bitwiseInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/conversionInstructions.3.2.ll b/test/Bitcode/conversionInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..4b3f273
--- /dev/null
+++ b/test/Bitcode/conversionInstructions.3.2.ll
@@ -0,0 +1,104 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread conversion instructions from\r
+; older bitcode files.\r
+\r
+define void @trunc(i32 %src){\r
+entry:\r
+; CHECK: %res1 = trunc i32 %src to i8\r
+  %res1 = trunc i32 %src to i8\r
+    \r
+  ret void\r
+}\r
+\r
+define void @zext(i32 %src){\r
+entry:\r
+; CHECK: %res1 = zext i32 %src to i64\r
+  %res1 = zext i32 %src to i64\r
+    \r
+  ret void\r
+}\r
+\r
+define void @sext(i32 %src){\r
+entry:\r
+; CHECK: %res1 = sext i32 %src to i64\r
+  %res1 = sext i32 %src to i64\r
+    \r
+  ret void\r
+}\r
+\r
+define void @fptrunc(double %src){\r
+entry:\r
+; CHECK: %res1 = fptrunc double %src to float\r
+  %res1 = fptrunc double %src to float\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fpext(float %src){\r
+entry:\r
+; CHECK: %res1 = fpext float %src to double\r
+  %res1 = fpext float %src to double\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fptoui(float %src){\r
+entry:\r
+; CHECK: %res1 = fptoui float %src to i32\r
+  %res1 = fptoui float %src to i32\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fptosi(float %src){\r
+entry:\r
+; CHECK: %res1 = fptosi float %src to i32\r
+  %res1 = fptosi float %src to i32\r
+  \r
+  ret void\r
+}\r
+\r
+define void @uitofp(i32 %src){\r
+entry:\r
+; CHECK: %res1 = uitofp i32 %src to float\r
+  %res1 = uitofp i32 %src to float\r
+  \r
+  ret void\r
+}\r
+\r
+define void @sitofp(i32 %src){\r
+entry:\r
+; CHECK: %res1 = sitofp i32 %src to float\r
+  %res1 = sitofp i32 %src to float\r
+  \r
+  ret void\r
+}\r
+\r
+define void @ptrtoint(i32* %src){\r
+entry:\r
+; CHECK: %res1 = ptrtoint i32* %src to i8\r
+  %res1 = ptrtoint i32* %src to i8\r
+  \r
+  ret void\r
+}\r
+\r
+define void @inttoptr(i32 %src){\r
+entry:\r
+; CHECK: %res1 = inttoptr i32 %src to i32*\r
+  %res1 = inttoptr i32 %src to i32*\r
+  \r
+  ret void\r
+}\r
+\r
+define void @bitcast(i32 %src1, i32* %src2){\r
+entry:\r
+; CHECK: %res1 = bitcast i32 %src1 to i32\r
+  %res1 = bitcast i32 %src1 to i32\r
+  \r
+; CHECK: %res2 = bitcast i32* %src2 to i64*\r
+  %res2 = bitcast i32* %src2 to i64*\r
+  \r
+  ret void\r
+}
\ No newline at end of file

diff --git a/test/Bitcode/conversionInstructions.3.2.ll.bc b/test/Bitcode/conversionInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..fabf7da
Binary files /dev/null and b/test/Bitcode/conversionInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/terminatorInstructions.3.2.ll b/test/Bitcode/terminatorInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..31e7896
--- /dev/null
+++ b/test/Bitcode/terminatorInstructions.3.2.ll
@@ -0,0 +1,47 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread terminator instructions from\r
+; older bitcode files.\r
+\r
+define i32 @condbr(i1 %cond){\r
+entry:\r
+; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel\r
+  br i1 %cond, label %TrueLabel, label %FalseLabel\r
+  \r
+  TrueLabel:\r
+  ret i32 1\r
+  \r
+  FalseLabel:\r
+  ret i32 0\r
+}\r
+\r
+define i32 @uncondbr(){\r
+entry:\r
+; CHECK: br label %uncondLabel\r
+  br label %uncondLabel\r
+  \r
+  uncondLabel:\r
+  ret i32 1\r
+}\r
+\r
+define i32 @indirectbr(i8* %Addr){\r
+entry:\r
+; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]\r
+  indirectbr i8* %Addr, [ label %bb1, label %bb2 ]\r
+  \r
+  bb1:\r
+  ret i32 1\r
+  \r
+  bb2:\r
+  ret i32 0\r
+}\r
+\r
+define void @unreachable(){\r
+entry:\r
+; CHECK: unreachable\r
+  unreachable\r
+  \r
+  ret void\r
+}\r
+\r

diff --git a/test/Bitcode/terminatorInstructions.3.2.ll.bc b/test/Bitcode/terminatorInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..9d92ead
Binary files /dev/null and b/test/Bitcode/terminatorInstructions.3.2.ll.bc differ

diff --git a/test/Bitcode/vectorInstructions.3.2.ll b/test/Bitcode/vectorInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..b24ef75
--- /dev/null
+++ b/test/Bitcode/vectorInstructions.3.2.ll
@@ -0,0 +1,34 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread vector operations of\r
+; older bitcode files.\r
+\r
+define void @extractelement(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0\r
+  %res1 = extractelement <2 x i8> %x1, i32 0\r
+  \r
+  ret void\r
+}\r
+\r
+define void @insertelement(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0\r
+  %res1 = insertelement <2 x i8> %x1, i8 0, i32 0\r
+  \r
+  ret void\r
+}\r
+\r
+define void @shufflevector(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>\r
+  %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>\r
+\r
+; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>\r
+  %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>\r
+  \r
+  ret void\r
+}\r
+\r
+\r

diff --git a/test/Bitcode/vectorInstructions.3.2.ll.bc b/test/Bitcode/vectorInstructions.3.2.ll.bc
new file mode 100644 (file)
index 0000000..b172703
Binary files /dev/null and b/test/Bitcode/vectorInstructions.3.2.ll.bc differ