Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/
9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922
91177308-0d34-0410-b5e6-
96231b3b80d8
// CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
bool LdStCop = LdStCopOpcode(Opcode);
// CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
bool LdStCop = LdStCopOpcode(Opcode);
+ bool RtOut = (Opcode == ARM::MRC || Opcode == ARM::MRC2);
+ if (RtOut) {
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ decodeRd(insn))));
+ ++OpIdx;
+ }
MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
if (LdStCop) {
// Unindex if P:W = 0b00 --> _OPTION variant
if (LdStCop) {
// Unindex if P:W = 0b00 --> _OPTION variant
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
if (PW) {
MI.addOperand(MCOperand::CreateReg(0));
if (PW) {
MI.addOperand(MCOperand::CreateReg(0));
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
ARM_AM::no_shift, IndexMode);
MI.addOperand(MCOperand::CreateImm(Offset));
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
ARM_AM::no_shift, IndexMode);
MI.addOperand(MCOperand::CreateImm(Offset));
} else {
MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
} else {
MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
}
} else {
MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
: GetCopOpc1(insn, NoGPR)));
}
} else {
MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
: GetCopOpc1(insn, NoGPR)));
- MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
- : MCOperand::CreateReg(
- getRegisterEnum(B, ARM::GPRRegClassID,
- decodeRd(insn))));
+ if (!RtOut) {
+ MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
+ : MCOperand::CreateReg(
+ getRegisterEnum(B, ARM::GPRRegClassID,
+ decodeRd(insn))));
+ ++OpIdx;
+ }
MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
getRegisterEnum(B, ARM::GPRRegClassID,
MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
getRegisterEnum(B, ARM::GPRRegClassID,
MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
if (!OneCopOpc) {
MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
if (!OneCopOpc) {
MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
# CHECK: streq r1, [sp], #-1567
0x1f 0x16 0xd 0x4
# CHECK: streq r1, [sp], #-1567
0x1f 0x16 0xd 0x4
+
+# CHECK: mrchs p2, #3, r11, c13, c6, #6
+0xd6 0xb2 0x7d 0x2e