Ensure that zero vectors are always v4i32, which forces them to CSE with

each other.  This implements CodeGen/PowerPC/vxor-canonicalize.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 99de51bf77d233cba2f487d0f3cd8ee52c374641..5a33d6ab7f621833e3254ddc2c15fec705a0f263 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -923,11 +923,19 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   case ISD::BUILD_VECTOR:
     // If this is a case we can't handle, return null and let the default
     // expansion code take care of it.  If we CAN select this case, return Op.
-    
-    // See if this is all zeros.
+
     // FIXME: We should handle splat(-0.0), and other cases here.
-    if (ISD::isBuildVectorAllZeros(Op.Val))
+
+    // See if this is all zeros.
+    if (ISD::isBuildVectorAllZeros(Op.Val)) {
+      // Canonicalize all zero vectors to be v4i32.
+      if (Op.getValueType() != MVT::v4i32) {
+        SDOperand Z = DAG.getConstant(0, MVT::i32);
+        Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
+        Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
+      }
       return Op;
+    }
     
     if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val ||    // vspltisb
         PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val ||    // vspltish

diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index 8377077303f372b4bc3fe88b5d6205220b145412..39304c876f5575130951e67a4b2f55d6c3bbc924 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -521,7 +521,7 @@ def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
                       
 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
                       "vxor $vD, $vD, $vD", VecFP,
-                      [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
+                      [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -544,9 +544,6 @@ def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
-def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
-def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
-def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
 
 // Loads.
 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
@@ -637,7 +634,7 @@ def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
           (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
 
 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
-          (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; 
+          (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 
 
 // Fused multiply add and multiply sub for packed float.  These are represented
 // separately from the real instructions above, for operations that must have