// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
if (MI.getOperand(0).getSymbolName()[0]) {
- llvm_report_error("JIT does not support inline asm!\n");
+ llvm_report_error("JIT does not support inline asm!");
}
break;
}
);
#else // Not an ARM host
void ARMCompilationCallback() {
- LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
+ LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
}
#endif
}
switch (getValueType(I->getType()).getSimpleVT()) {
default:
- LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.\n");
+ LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs)
if (InFlag.getNode())
CallOperands.push_back(InFlag);
else
- LLVM_UNREACHABLE("this should never happen!\n");
+ LLVM_UNREACHABLE("this should never happen!");
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1;
} else {
- LLVM_UNREACHABLE(
- "sorry, I don't know how to store this sort of reg\n");
+ LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
.addReg(IA64::r0);
} else {
LLVM_UNREACHABLE(
- "sorry, I don't know how to load this sort of reg from the stack\n");
+ "sorry, I don't know how to load this sort of reg from the stack");
}
}
Opc = IA64::LD1;
} else {
LLVM_UNREACHABLE(
- "sorry, I don't know how to load this sort of reg\n");
+ "sorry, I don't know how to load this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
else if (Subtarget->isTargetELF())
O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
else
- LLVM_UNREACHABLE( "Don't know how to print PIC label!\n");
+ LLVM_UNREACHABLE( "Don't know how to print PIC label!");
}
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
#else // Not an i386 host
void X86CompilationCallback() {
- LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n");
+ LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
}
#endif
}
TLSOffset -= size;
return TLSOffset;
#else
- LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!\n");
+ LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
return 0;
#endif
}
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented");
}
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented");
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
.addReg(ScratchReg, RegState::Kill);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
} else {
switch (MI.getOpcode()) {
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
}
} else {
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ LLVM_UNREACHABLE("Unexpected Opcode");
}
}
// Erase old instruction.
template<class ConstantClass, class TypeClass>
struct VISIBILITY_HIDDEN ConvertConstantType {
static void convert(ConstantClass *OldC, const TypeClass *NewTy) {
- LLVM_UNREACHABLE("This type cannot be converted!\n");
+ LLVM_UNREACHABLE("This type cannot be converted!");
}
};