Add support for scalarizing ctlz_zero_undef
authorPetar Jovanovic <petar.jovanovic@imgtec.com>
Wed, 30 Jul 2014 00:44:03 +0000 (00:44 +0000)
committerPetar Jovanovic <petar.jovanovic@imgtec.com>
Wed, 30 Jul 2014 00:44:03 +0000 (00:44 +0000)
Fix the missing case in ScalarizeVectorResult() that was exposed with
libclcore.bc in Android.

Differential Revision: http://reviews.llvm.org/D4645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214266 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
test/CodeGen/Mips/ctlz-v.ll [new file with mode: 0644]

index 34dbe706ad16720f65fe11e25642fa8d834647ca..3b7f7968a7aab168395cf3a68fd1422ec9efa047 100644 (file)
@@ -69,6 +69,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::ANY_EXTEND:
   case ISD::BSWAP:
   case ISD::CTLZ:
+  case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
   case ISD::FABS:
diff --git a/test/CodeGen/Mips/ctlz-v.ll b/test/CodeGen/Mips/ctlz-v.ll
new file mode 100644 (file)
index 0000000..270f404
--- /dev/null
@@ -0,0 +1,19 @@
+; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
+
+define <2 x i32> @ctlzv2i32(<2 x i32> %x) {
+entry:
+; MIPS32: clz     $2, $4
+; MIPS32: jr      $ra
+; MIPS32: clz     $3, $5
+
+; MIPS64: clz     $2, $4
+; MIPS64: jr      $ra
+; MIPS64: clz     $3, $5
+
+  %ret = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
+  ret <2 x i32> %ret
+}
+