Fix more MC layering violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8eeca013ffb080d847fed5447235ab0b0a4317a2..6883fcbe2e3586348514e263335b83c632b317d1 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -153,6 +153,11 @@ public:
 };
 } // end anonymous namespace
 
+namespace llvm {
+  // FIXME: TableGen this?
+  extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
+}
+
 namespace {
 
 /// ARMOperand - Instances of this class represent a parsed ARM machine
@@ -971,9 +976,11 @@ public:
                 SMLoc StartLoc, SMLoc EndLoc) {
     KindTy Kind = RegisterList;
 
-    if (ARM::DPRRegClass.contains(Regs.front().first))
+    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
+        contains(Regs.front().first))
       Kind = DPRRegisterList;
-    else if (ARM::SPRRegClass.contains(Regs.front().first))
+    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
+             contains(Regs.front().first))
       Kind = SPRRegisterList;
 
     ARMOperand *Op = new ARMOperand(Kind);