Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version

of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index eb3ed3bf30ecc7ce6a7b687544710a45e9b58ea2..9f6822b69721deb4ecd56b541758b84234f21684 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -657,6 +657,32 @@ multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
    }
 }
 
+// SXTB16 and UXTB16 do not need the .w qualifier.
+multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> {
+  def r     : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+                  opc, "\t$dst, $src",
+                 [(set GPR:$dst, (opnode GPR:$src))]> {
+     let Inst{31-27} = 0b11111;
+     let Inst{26-23} = 0b0100;
+     let Inst{22-20} = opcod;
+     let Inst{19-16} = 0b1111; // Rn
+     let Inst{15-12} = 0b1111;
+     let Inst{7} = 1;
+     let Inst{5-4} = 0b00; // rotate
+   }
+  def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
+                  opc, "\t$dst, $src, ror $rot",
+                 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
+     let Inst{31-27} = 0b11111;
+     let Inst{26-23} = 0b0100;
+     let Inst{22-20} = opcod;
+     let Inst{19-16} = 0b1111; // Rn
+     let Inst{15-12} = 0b1111;
+     let Inst{7} = 1;
+     let Inst{5-4} = {?,?}; // rotate
+   }
+}
+
 // DO variant - disassembly only, no pattern
 
 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
@@ -1260,7 +1286,7 @@ defm t2UXTB   : T2I_unary_rrot<0b101, "uxtb",
                                UnOpFrag<(and node:$Src, 0x000000FF)>>;
 defm t2UXTH   : T2I_unary_rrot<0b001, "uxth",
                                UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
-defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
+defm t2UXTB16 : T2I_unary_rrot_nw<0b011, "uxtb16",
                                UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
 
 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),

diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 4e23f5356cf9407d1db43844915cf6111de595cc..91598cdc961a06d9e131c0ffa0146050cf7695d6 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -2,14 +2,14 @@
 
 define i32 @test1(i32 %x) {
 ; CHECK: test1
-; CHECK: uxtb16.w  r0, r0
+; CHECK: uxtb16  r0, r0
        %tmp1 = and i32 %x, 16711935            ; <i32> [#uses=1]
        ret i32 %tmp1
 }
 
 define i32 @test2(i32 %x) {
 ; CHECK: test2
-; CHECK: uxtb16.w  r0, r0, ror #8
+; CHECK: uxtb16  r0, r0, ror #8
        %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
        ret i32 %tmp2
@@ -17,7 +17,7 @@ define i32 @test2(i32 %x) {
 
 define i32 @test3(i32 %x) {
 ; CHECK: test3
-; CHECK: uxtb16.w  r0, r0, ror #8
+; CHECK: uxtb16  r0, r0, ror #8
        %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
        ret i32 %tmp2
@@ -25,7 +25,7 @@ define i32 @test3(i32 %x) {
 
 define i32 @test4(i32 %x) {
 ; CHECK: test4
-; CHECK: uxtb16.w  r0, r0, ror #8
+; CHECK: uxtb16  r0, r0, ror #8
        %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
        %tmp6 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
        ret i32 %tmp6
@@ -33,7 +33,7 @@ define i32 @test4(i32 %x) {
 
 define i32 @test5(i32 %x) {
 ; CHECK: test5
-; CHECK: uxtb16.w  r0, r0, ror #8
+; CHECK: uxtb16  r0, r0, ror #8
        %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
        ret i32 %tmp2
@@ -41,7 +41,7 @@ define i32 @test5(i32 %x) {
 
 define i32 @test6(i32 %x) {
 ; CHECK: test6
-; CHECK: uxtb16.w  r0, r0, ror #16
+; CHECK: uxtb16  r0, r0, ror #16
        %tmp1 = lshr i32 %x, 16         ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 255              ; <i32> [#uses=1]
        %tmp4 = shl i32 %x, 16          ; <i32> [#uses=1]
@@ -52,7 +52,7 @@ define i32 @test6(i32 %x) {
 
 define i32 @test7(i32 %x) {
 ; CHECK: test7
-; CHECK: uxtb16.w  r0, r0, ror #16
+; CHECK: uxtb16  r0, r0, ror #16
        %tmp1 = lshr i32 %x, 16         ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 255              ; <i32> [#uses=1]
        %tmp4 = shl i32 %x, 16          ; <i32> [#uses=1]
@@ -63,7 +63,7 @@ define i32 @test7(i32 %x) {
 
 define i32 @test8(i32 %x) {
 ; CHECK: test8
-; CHECK: uxtb16.w  r0, r0, ror #24
+; CHECK: uxtb16  r0, r0, ror #24
        %tmp1 = shl i32 %x, 8           ; <i32> [#uses=1]
        %tmp2 = and i32 %tmp1, 16711680         ; <i32> [#uses=1]
        %tmp5 = lshr i32 %x, 24         ; <i32> [#uses=1]
@@ -73,7 +73,7 @@ define i32 @test8(i32 %x) {
 
 define i32 @test9(i32 %x) {
 ; CHECK: test9
-; CHECK: uxtb16.w  r0, r0, ror #24
+; CHECK: uxtb16  r0, r0, ror #24
        %tmp1 = lshr i32 %x, 24         ; <i32> [#uses=1]
        %tmp4 = shl i32 %x, 8           ; <i32> [#uses=1]
        %tmp5 = and i32 %tmp4, 16711680         ; <i32> [#uses=1]
@@ -86,7 +86,7 @@ define i32 @test10(i32 %p0) {
 ; CHECK: mov.w r1, #16253176
 ; CHECK: and.w r0, r1, r0, lsr #7
 ; CHECK: lsrs  r1, r0, #5
-; CHECK: uxtb16.w  r1, r1
+; CHECK: uxtb16  r1, r1
 ; CHECK: orr.w r0, r1, r0
 
        %tmp1 = lshr i32 %p0, 7         ; <i32> [#uses=1]