[Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202604 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 0aba1f28cd1ab89df4cccd7b284958c2a58ecf45..65d9228ad94e712645d471965f9e9455f71d12c0 100644 (file)
--- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -676,7 +676,7 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
           Op = SparcOperand::CreateToken("%icc", S);
         break;
 
           Op = SparcOperand::CreateToken("%icc", S);
         break;
 

-      case Sparc::FCC:
+      case Sparc::FCC0:

         assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
         Op = SparcOperand::CreateToken("%fcc0", S);
         break;
         assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
         Op = SparcOperand::CreateToken("%fcc0", S);
         break;


@@ -783,7 +783,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
         && !name.substr(3).getAsInteger(10, intVal)
         && intVal < 4) {
       // FIXME: check 64bit and  handle %fcc1 - %fcc3
         && !name.substr(3).getAsInteger(10, intVal)
         && intVal < 4) {
       // FIXME: check 64bit and  handle %fcc1 - %fcc3

-      RegNo = Sparc::FCC;
+      RegNo = Sparc::FCC0;

       RegKind = SparcOperand::rk_CCReg;
       return true;
     }
       RegKind = SparcOperand::rk_CCReg;
       return true;
     }

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index dec9c294766cf7d0b060b1fd71a196a98df361be..690a5bf818471d31d76d8283acf9eb6cd926ef63 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -354,7 +354,7 @@ let Uses = [ICC], usesCustomInserter = 1 in {
             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
 }
 
             [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
 }
 

-let usesCustomInserter = 1, Uses = [FCC] in {
+let usesCustomInserter = 1, Uses = [FCC0] in {

 
   def SELECT_CC_Int_FCC
    : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
 
   def SELECT_CC_Int_FCC
    : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),


@@ -645,7 +645,7 @@ multiclass FPredBranch {
 }
 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
 
 }
 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
 

-let Uses = [FCC] in {
+let Uses = [FCC0] in {

   def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
                               "fb$cond $imm22",
                               [(SPbrfcc bb:$imm22, imm:$cond)]>;
   def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
                               "fb$cond $imm22",
                               [(SPbrfcc bb:$imm22, imm:$cond)]>;


@@ -864,7 +864,7 @@ def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
 // This behavior is modeled with a forced noop after the instruction in
 // DelaySlotFiller.
 
 // This behavior is modeled with a forced noop after the instruction in
 // DelaySlotFiller.
 

-let Defs = [FCC] in {
+let Defs = [FCC0] in {

   def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
                    (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
                    "fcmps $rs1, $rs2",
   def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
                    (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
                    "fcmps $rs1, $rs2",


@@ -931,7 +931,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
                     (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
   }
 
                     (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
   }
 

-  let Uses = [FCC], cc = 0b000 in {
+  let Uses = [FCC0], cc = 0b000 in {

     def MOVFCCrr
       : F4_1<0b101100, (outs IntRegs:$rd),
              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
     def MOVFCCrr
       : F4_1<0b101100, (outs IntRegs:$rd),
              (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),


@@ -964,7 +964,7 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
                Requires<[HasHardQuad]>;
   }
 
                Requires<[HasHardQuad]>;
   }
 

-  let Uses = [FCC], opf_cc = 0b000 in {
+  let Uses = [FCC0], opf_cc = 0b000 in {

     def FMOVS_FCC
       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
     def FMOVS_FCC
       : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
              (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 4a1e2f1b8e5c8f19b574ef1fe0c6dde12f1b3a76..2cadff1ef7bb5d18aa9b2a52ec65bc16c69c0c5a 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -16,7 +16,8 @@ class SparcReg<bits<16> Enc, string n> : Register<n> {
   let Namespace = "SP";
 }
 
   let Namespace = "SP";
 }
 

-class SparcCtrlReg<string n>: Register<n> {
+class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
+  let HWEncoding = Enc;

   let Namespace = "SP";
 }
 
   let Namespace = "SP";
 }
 


@@ -49,11 +50,12 @@ class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
 }
 
 // Control Registers
 }
 
 // Control Registers

-def ICC : SparcCtrlReg<"ICC">; // This represents icc and xcc in 64-bit code.
-def FCC : SparcCtrlReg<"FCC">;
+def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
+foreach I = 0-3 in
+  def FCC#I : SparcCtrlReg<I, "FCC"#I>;

 
 // Y register
 
 // Y register

-def Y : SparcCtrlReg<"Y">, DwarfRegNum<[64]>;
+def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;

 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;


@@ -204,3 +206,6 @@ def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
 
 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
 
 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;

+
+// Floating point control register classes.
+def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;