BypassTable += " 0, // No itinerary\n";
unsigned StageCount = 1, OperandCycleCount = 1;
- unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1;
std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
// Next record
if (NStages > 0) {
FindStage = ItinStageMap[ItinStageString];
if (FindStage == 0) {
- // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // index
- StageTable += ItinStageString + ", // " + itostr(ItinStageEnum) + "\n";
+ // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
+ StageTable += ItinStageString + ", // " + itostr(StageCount);
+ if (NStages > 1)
+ StageTable += "-" + itostr(StageCount + NStages - 1);
+ StageTable += "\n";
// Record Itin class number.
ItinStageMap[ItinStageString] = FindStage = StageCount;
StageCount += NStages;
- ItinStageEnum++;
}
}
FindOperandCycle = ItinOperandMap[ItinOperandString];
if (FindOperandCycle == 0) {
// Emit as cycle, // index
- OperandCycleTable += ItinOperandCycleString + ", // " +
- itostr(ItinOperandCycleEnum) + "\n";
+ OperandCycleTable += ItinOperandCycleString + ", // ";
+ std::string OperandIdxComment = itostr(OperandCycleCount);
+ if (NOperandCycles > 1)
+ OperandIdxComment += "-"
+ + itostr(OperandCycleCount + NOperandCycles - 1);
+ OperandCycleTable += OperandIdxComment + "\n";
// Record Itin class number.
ItinOperandMap[ItinOperandCycleString] =
FindOperandCycle = OperandCycleCount;
-
// Emit as bypass, // index
- BypassTable += ItinBypassString + ", // " +
- itostr(ItinOperandCycleEnum) + "\n";
-
+ BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
OperandCycleCount += NOperandCycles;
- ItinOperandCycleEnum++;
}
}
//
// EmitProcessorData - Generate data for processor itineraries.
//
-void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
- std::vector<std::vector<InstrItinerary> > &ProcList) {
+void SubtargetEmitter::
+EmitProcessorData(raw_ostream &OS,
+ std::vector<Record*> &ItinClassList,
+ std::vector<std::vector<InstrItinerary> > &ProcList) {
// Get an iterator for processor itinerary stages
std::vector<std::vector<InstrItinerary> >::iterator
ProcListIter = ProcList.begin();
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
+ assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
InstrItinerary &Intinerary = ItinList[j];
Intinerary.LastOperandCycle << " }";
}
- OS << ", // " << j << "\n";
+ OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n";
}
// End processor itinerary table
EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap,
ItinClassList, ProcList);
// Emit the processor itinerary data
- EmitProcessorData(OS, ProcList);
+ EmitProcessorData(OS, ItinClassList, ProcList);
// Emit the processor lookup data
EmitProcessorLookup(OS);
}