Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95548 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 2ba586655160674c226cc8ea1f6f68615651e956..7fcd98c8c13cb1046c1d6ea5d799e438c4bc8ad7 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -252,6 +252,13 @@ def VMOVRRD  : AVConv3I<0b11000101, 0b1011,
   let Inst{7-6} = 0b00;
 }
 
+def VMOVRRS  : AVConv3I<0b11000101, 0b1010,
+                      (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
+                 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
+                 [/* For disassembly only; pattern left blank */]> {
+  let Inst{7-6} = 0b00;
+}
+
 // FMDHR: GPR -> SPR
 // FMDLR: GPR -> SPR
 
@@ -262,6 +269,13 @@ def VMOVDRR : AVConv5I<0b11000100, 0b1011,
   let Inst{7-6} = 0b00;
 }
 
+def VMOVSRR : AVConv5I<0b11000100, 0b1010,
+                     (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
+                IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
+                [/* For disassembly only; pattern left blank */]> {
+  let Inst{7-6} = 0b00;
+}
+
 // FMRDH: SPR -> GPR
 // FMRDL: SPR -> GPR
 // FMRRS: SPR -> GPR