remove done item

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27778 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt
index 2887b798b0e26a16dac1253991775ad5e537cce3..2d91986f83fa818e293a82594f230bcc4cb93379 100644 (file)
--- a/lib/Target/PowerPC/README_ALTIVEC.txt
+++ b/lib/Target/PowerPC/README_ALTIVEC.txt
@@ -5,8 +5,8 @@ registers, to generate better spill code.
 
 //===----------------------------------------------------------------------===//
 
-Altivec support.  The first should be a single lvx from the constant pool, the
-second should be a xor/stvx:
+The first should be a single lvx from the constant pool, the second should be 
+a xor/stvx:
 
 void foo(void) {
   int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 17, 1, 1, 1, 1 };
@@ -39,23 +39,6 @@ a load/store/lve*x sequence.
 
 //===----------------------------------------------------------------------===//
 
-There are a wide range of vector constants we can generate with combinations of
-altivec instructions.
-
-Examples, these work with all widths:
-  Splat(+/- 16,18,20,22,24,28,30):  t = vspliti I/2,  r = t+t
-  Splat(+/- 17,19,21,23,25,29):     t = vsplti +/-15, t2 = vsplti I-15, r=t + t2
-  Splat(31):                        t = vsplti FB,  r = srl t,t
-  Splat(256):  t = vsplti 1, r = vsldoi t, t, 1
-
-Lots more are listed here:
-http://www.informatik.uni-bremen.de/~hobold/AltiVec.html
-
-This should be added to the ISD::BUILD_VECTOR case in 
-PPCTargetLowering::LowerOperation.
-
-//===----------------------------------------------------------------------===//
-
 FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
 
 //===----------------------------------------------------------------------===//