Enable on-demand fast-isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index cc8c3c70ac29c380c21e295af979b4adb2757759..2d6b78840f5f93543f0ccb84c5413c64a389c930 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -161,7 +161,10 @@ unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
       }
     }
   } else if (const Operator *Op = dyn_cast<Operator>(V)) {
-    if (!SelectOperator(Op, Op->getOpcode())) return 0;
+    if (!SelectOperator(Op, Op->getOpcode()))
+      if (!isa<Instruction>(Op) ||
+          !TargetSelectInstruction(cast<Instruction>(Op)))
+        return 0;
     Reg = lookUpRegForValue(Op);
   } else if (isa<UndefValue>(V)) {
     Reg = createResultReg(TLI.getRegClassFor(VT));

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 3b0ef18dd85ee1eaa8079b14d7c7839106bf7b55..0848e46c0ef44277d5c3b5fa8729ec8816c84186 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -709,6 +709,12 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
       FastIS->startNewBlock(BB);
       // Do FastISel on as many instructions as possible.
       for (; BI != End; ++BI) {
+        // Defer instructions with no side effects; they'll be emitted
+        // on-demand later.
+        if (BI->isSafeToSpeculativelyExecute() &&
+            !FuncInfo->ValueMap.count(BI))
+          continue;
+
         // Try to select the instruction with FastISel.
         if (FastIS->SelectInstruction(BI))
           continue;

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 1c700b290a661583171acca9dfbb67e8c66d3ab8..6733f80d501f82cdde8daef3a5d0067e0e272913 100644 (file)
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -935,7 +935,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
       if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
           CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
         const MachineInstr *SetMI = 0;
-        unsigned Reg = lookUpRegForValue(EI);
+        unsigned Reg = getRegForValue(EI);
 
         for (MachineBasicBlock::const_reverse_iterator
                RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {

diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll
index 35f7a72a285c09517bad30b0611ec15edad9364e..7759bb056892e353d2ec66f05507ff690167ee19 100644 (file)
--- a/test/CodeGen/X86/fast-isel-shift-imm.ll
+++ b/test/CodeGen/X86/fast-isel-shift-imm.ll
@@ -1,7 +1,8 @@
 ; RUN: llc < %s -march=x86 -O0 | grep {sarl    \$80, %eax}
 ; PR3242
 
-define i32 @foo(i32 %x) nounwind {
+define void @foo(i32 %x, i32* %p) nounwind {
   %y = ashr i32 %x, 50000
-  ret i32 %y
+  store i32 %y, i32* %p
+  ret void
 }