def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
"PadShortFunctions", "true",
"Pad short functions">;
+def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
+ "CallRegIndirect", "true",
+ "Call register indirect">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
def : ProcessorModel<"atom", AtomModel,
[ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
- FeatureSlowDivide, FeaturePadShortFunctions]>;
+ FeatureSlowDivide,
+ FeatureCallRegIndirect,
+ FeaturePadShortFunctions]>;
// "Arrandale" along with corei3 and corei5
def : ProcessorModel<"corei7", SandyBridgeModel,
InFlag = Chain.getValue(1);
}
+ // Use indirect reference through register, when CALL uses a memory reference.
+ if (Subtarget->callRegIndirect() &&
+ Callee.getOpcode() == ISD::LOAD) {
+ const TargetRegisterClass *AddrRegClass =
+ getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ unsigned VReg = MRI.createVirtualRegister(AddrRegClass);
+ SDValue tempValue = DAG.getCopyFromReg(Callee,
+ dl, VReg, Callee.getValueType());
+ Chain = DAG.getCopyToReg(Chain, dl, VReg, tempValue, InFlag);
+ InFlag = Chain.getValue(1);
+ }
+
Ops.push_back(Chain);
Ops.push_back(Callee);
HasSlowDivide = false;
PostRAScheduler = false;
PadShortFunctions = false;
+ CallRegIndirect = false;
stackAlignment = 4;
// FIXME: this is a known good value for Yonah. How about others?
MaxInlineSizeThreshold = 128;
/// a stall when returning too early.
bool PadShortFunctions;
+ /// CallRegIndirect - True if the Calls with memory reference should be converted
+ /// to a register-based indirect call.
+ bool CallRegIndirect;
+
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment;
bool useLeaForSP() const { return UseLeaForSP; }
bool hasSlowDivide() const { return HasSlowDivide; }
bool padShortFunctions() const { return PadShortFunctions; }
+ bool callRegIndirect() const { return CallRegIndirect; }
bool isAtom() const { return X86ProcFamily == IntelAtom; }
--- /dev/null
+; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM32 %s
+; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck -check-prefix=ATOM-NOT32 %s
+; RUN: llc < %s -mcpu=atom -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM64 %s
+; RUN: llc < %s -mcpu=core2 -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM-NOT64 %s
+
+
+; fn_ptr.ll
+%class.A = type { i32 (...)** }
+
+define i32 @test1() #0 {
+ ;ATOM: test1
+entry:
+ %call = tail call %class.A* @_Z3facv()
+ %0 = bitcast %class.A* %call to void (%class.A*)***
+ %vtable = load void (%class.A*)*** %0, align 8
+ %1 = load void (%class.A*)** %vtable, align 8
+ ;ATOM32: movl (%ecx), %ecx
+ ;ATOM32: calll *%ecx
+ ;ATOM-NOT32: calll *(%ecx)
+ ;ATOM64: movq (%rcx), %rcx
+ ;ATOM64: callq *%rcx
+ ;ATOM-NOT64: callq *(%rcx)
+ tail call void %1(%class.A* %call)
+ ret i32 0
+}
+
+declare %class.A* @_Z3facv() #1
+
+; virt_fn.ll
+@p = external global void (i32)**
+
+define i32 @test2() #0 {
+ ;ATOM: test2
+entry:
+ %0 = load void (i32)*** @p, align 8
+ %1 = load void (i32)** %0, align 8
+ ;ATOM32: movl (%eax), %eax
+ ;ATOM32: calll *%eax
+ ;ATOM-NOT: calll *(%eax)
+ ;ATOM64: movq (%rax), %rax
+ ;ATOM64: callq *%rax
+ ;ATOM-NOT64: callq *(%rax)
+ tail call void %1(i32 2)
+ ret i32 0
+}