Thumb parsing and encoding for STM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 931bd365248b33a7c777d8db635c67f19d36b2ba..40efea74545cd89208d426a54025b39a32ed64da 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3149,6 +3149,13 @@ validateInstruction(MCInst &Inst,
                    "registers must be in range r0-r7 or lr");
     break;
   }
+  case ARM::tSTMIA_UPD: {
+    bool listContainsBase;
+    if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
+      return Error(Operands[4]->getStartLoc(),
+                   "registers must be in range r0-r7");
+    break;
+  }
   }
 
   return false;

diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 020bc935d1750a379efd1d9905b3360d5e9c5ff7..741fe85f10dcf617518da0c743b0e6dc496f5cad 100644 (file)
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -425,3 +425,13 @@ _func:
 
 @ CHECK: setend        be                      @ encoding: [0x58,0xb6]
 @ CHECK: setend        le                      @ encoding: [0x50,0xb6]
+
+
+@------------------------------------------------------------------------------
+@ STM
+@------------------------------------------------------------------------------
+        stm r1!, {r2, r6}
+        stm r1!, {r1, r2, r3, r7}
+
+@ CHECK: stm   r1!, {r2, r6}           @ encoding: [0x44,0xc1]
+@ CHECK: stm   r1!, {r1, r2, r3, r7}   @ encoding: [0x8e,0xc1]

diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s
index 55b062e39932985c711cd68ef9ae9b1f46d76486..604127a64294b15927e7ceb6239a2b56913ffdde 100644 (file)
--- a/test/MC/ARM/thumb-diagnostics.s
+++ b/test/MC/ARM/thumb-diagnostics.s
@@ -68,6 +68,15 @@ error: invalid operand for instruction
 @ CHECK-ERRORS:              ^
 
 
+@ Invalid writeback and register lists for STM
+        stm r1, {r2, r6}
+        stm r1!, {r2, r9}
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS:         stm r1, {r2, r6}
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: registers must be in range r0-r7
+@ CHECK-ERRORS:         stm r1!, {r2, r9}
+@ CHECK-ERRORS:                  ^
 
 @ Out of range immediates for LSL instruction.
         lsls r4, r5, #-1