Implement ISD::TRAP support on PPC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index fcf235ccd11c205b8cd388187c462bb7b9efaf47..2dec8d61b5bf9834caf6f4568e47e92d731481cc 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -183,9 +183,12 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   setOperationAction(ISD::ConstantPool,  MVT::i64, Custom);
   setOperationAction(ISD::JumpTable,     MVT::i64, Custom);
   
-  // RET must be custom lowered, to meet ABI requirements
+  // RET must be custom lowered, to meet ABI requirements.
   setOperationAction(ISD::RET               , MVT::Other, Custom);
 
+  // TRAP is legal.
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+    
   // VASTART needs to be custom lowered to use the VarArgsFrameIndex
   setOperationAction(ISD::VASTART           , MVT::Other, Custom);
   

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 0355d950ded7d64d1c1c3e2ca1d5273282df5642..b08f18618f3c9593c385dbc0f25c28bd38159676 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -298,6 +298,17 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = 0;
 }
 
+class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin, list<dag> pattern> 
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  let Pattern = pattern;
+  let Inst{6-10}  = 31;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern> 
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 3e0e6055e67fe0ddb9653b896c25711477c5ab10..b4b6080a04e1eed76ad349731cb752e3de1768f7 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -575,6 +575,9 @@ def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
                    [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
                    isDOT;
 
+let isBarrier = 1, hasCtrlDep = 1 in
+def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
+
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //

diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt
index 55baf8d270ade8a0387ba6f00c02d383fc5b9373..e5d4002846ebde813221a819f09791f386d53699 100644 (file)
--- a/lib/Target/PowerPC/README.txt
+++ b/lib/Target/PowerPC/README.txt
@@ -3,7 +3,6 @@
 TODO:
 * gpr0 allocation
 * implement do-loop -> bdnz transform
-* Implement __builtin_trap (ISD::TRAP) as 'tw 31, 0, 0' aka 'trap'.
 * lmw/stmw pass a la arm load store optimizer for prolog/epilog
 
 ===-------------------------------------------------------------------------===