[WebAssembly] Rename BR_IF_ to BR_IF

With MC-based instruction printing, we no longer need instruction names to
mangle in hints about how they should be printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252987 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/WebAssembly/WebAssemblyISD.def b/lib/Target/WebAssembly/WebAssemblyISD.def
index 36b6d9c68c837657818c5450857f82a001a50efc..52c37757cdb8ec914825a61e624833a8d28322fa 100644 (file)
--- a/lib/Target/WebAssembly/WebAssemblyISD.def
+++ b/lib/Target/WebAssembly/WebAssemblyISD.def
@@ -19,7 +19,7 @@ HANDLE_NODETYPE(CALL0)
 HANDLE_NODETYPE(RETURN)
 HANDLE_NODETYPE(ARGUMENT)
 HANDLE_NODETYPE(Wrapper)
 HANDLE_NODETYPE(RETURN)
 HANDLE_NODETYPE(ARGUMENT)
 HANDLE_NODETYPE(Wrapper)

-HANDLE_NODETYPE(BR_IF_)
+HANDLE_NODETYPE(BR_IF)

 HANDLE_NODETYPE(SWITCH)
 
 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
 HANDLE_NODETYPE(SWITCH)
 
 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...

diff --git a/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/lib/Target/WebAssembly/WebAssemblyInstrControl.td
index b5140324d4f1b25a671c4f0db15deb6ece00b719..5883553e8f19fbed601d50a4369bc656fb914c47 100644 (file)
--- a/lib/Target/WebAssembly/WebAssemblyInstrControl.td
+++ b/lib/Target/WebAssembly/WebAssemblyInstrControl.td
@@ -13,9 +13,9 @@
 //===----------------------------------------------------------------------===//
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
 //===----------------------------------------------------------------------===//
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {

-def BR_IF_ : I<(outs), (ins bb_op:$dst, I32:$a),
-               [(brcond I32:$a, bb:$dst)],
-               "br_if $dst, $a">;
+def BR_IF : I<(outs), (ins bb_op:$dst, I32:$a),
+              [(brcond I32:$a, bb:$dst)],
+              "br_if $dst, $a">;

 let isBarrier = 1 in {
 def BR   : I<(outs), (ins bb_op:$dst),
              [(br bb:$dst)],
 let isBarrier = 1 in {
 def BR   : I<(outs), (ins bb_op:$dst),
              [(br bb:$dst)],

diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index a18357da19ea41a916de3ce661f35eed143caab6..fe27b1ac669bdb3f2258bb6e92d92dea6263a120 100644 (file)
--- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -51,7 +51,7 @@ bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
     default:
       // Unhandled instruction; bail out.
       return true;
     default:
       // Unhandled instruction; bail out.
       return true;

-    case WebAssembly::BR_IF_:
+    case WebAssembly::BR_IF:

       if (HaveCond)
         return true;
       Cond.push_back(MI.getOperand(1));
       if (HaveCond)
         return true;
       Cond.push_back(MI.getOperand(1));


@@ -104,7 +104,7 @@ unsigned WebAssemblyInstrInfo::InsertBranch(
     return 1;
   }
 
     return 1;
   }
 

-  BuildMI(&MBB, DL, get(WebAssembly::BR_IF_))
+  BuildMI(&MBB, DL, get(WebAssembly::BR_IF))

       .addMBB(TBB)
       .addOperand(Cond[0]);
   if (!FBB)
       .addMBB(TBB)
       .addOperand(Cond[0]);
   if (!FBB)