ARM64: Remove unused helper function, make others static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205112 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/ARM64ConditionalCompares.cpp b/lib/Target/ARM64/ARM64ConditionalCompares.cpp
index fd9abd64214c329bc5c48cb2d7623b52cb4cf595..b495afaa38b71dd4efb58df9700d22ed85ff2c2d 100644 (file)
--- a/lib/Target/ARM64/ARM64ConditionalCompares.cpp
+++ b/lib/Target/ARM64/ARM64ConditionalCompares.cpp
@@ -266,7 +266,7 @@ bool SSACCmpConv::isDeadDef(unsigned DstReg) {
 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
 // corresponding to TBB.
 // Return
-bool parseCond(ArrayRef<MachineOperand> Cond, ARM64CC::CondCode &CC) {
+static bool parseCond(ArrayRef<MachineOperand> Cond, ARM64CC::CondCode &CC) {
   // A normal br.cond simply has the condition code.
   if (Cond[0].getImm() != -1) {
     assert(Cond.size() == 1 && "Unknown Cond array format");

diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
index 76096088dfd450200b5b8f40b3c2ea8ca7f5f1d1..d8c51691d08399b3af0970bb7ee25a38b242b226 100644 (file)
--- a/lib/Target/ARM64/ARM64ISelLowering.cpp
+++ b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -4939,8 +4939,8 @@ FailedModImm:
 // Specialized code to quickly find if PotentialBVec is a BuildVector that
 // consists of only the same constant int value, returned in reference arg
 // ConstVal
-bool isAllConstantBuildVector(const SDValue &PotentialBVec,
-                              uint64_t &ConstVal) {
+static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
+                                     uint64_t &ConstVal) {
   BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
   if (!Bvec)
     return false;
@@ -6613,45 +6613,6 @@ static SDValue tryCombineFixedPointConvert(SDNode *N,
   return SDValue();
 }
 
-// Normalise extract_subvectors that extract the high V64 of a V128. If
-// the type of the extract_subvector is anything other than v1i64,
-// create a new exact with type v1i64. This is so that the
-// extract_subvector matches the extract_high PatFrag in tablegen.
-SDValue normalizeExtractHigh(SDNode *N, SelectionDAG &DAG) {
-  // Look through bitcasts.
-  while (N->getOpcode() == ISD::BITCAST)
-    N = N->getOperand(0).getNode();
-
-  if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR)
-    return SDValue();
-
-  uint64_t idx = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
-
-  EVT SrcVT = N->getOperand(0).getValueType();
-  unsigned SrcElts = SrcVT.getVectorNumElements();
-  unsigned DstElts = N->getValueType(0).getVectorNumElements();
-
-  if ((SrcElts == 2 * DstElts) && (idx == DstElts)) {
-
-    // If this is already a v1i64 extract, just return it.
-    if (DstElts == 1)
-      return SDValue(N, 0);
-
-#ifndef NDEBUG
-    unsigned SrcBits = SrcVT.getVectorElementType().getSizeInBits();
-    assert(SrcElts * SrcBits == 128 && "Not an extract from a wide vector");
-#endif
-
-    SDValue Bitcast =
-        DAG.getNode(ISD::BITCAST, SDLoc(N), MVT::v2i64, N->getOperand(0));
-
-    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), MVT::v1i64, Bitcast,
-                       DAG.getConstant(1, MVT::i64));
-  }
-
-  return SDValue();
-}
-
 // AArch64 high-vector "long" operations are formed by performing the non-high
 // version on an extract_subvector of each operand which gets the high half:
 //

diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
index eba53b2f86dbeff350a5179a91b429a237780bee..8d54412f5316422352aa192545901c4e9b5b799d 100644 (file)
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
@@ -73,9 +73,9 @@ static MCAsmInfo *createARM64MCAsmInfo(const MCRegisterInfo &MRI,
   return MAI;
 }
 
-MCCodeGenInfo *createARM64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                        CodeModel::Model CM,
-                                        CodeGenOpt::Level OL) {
+static MCCodeGenInfo *createARM64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
+                                               CodeModel::Model CM,
+                                               CodeGenOpt::Level OL) {
   Triple TheTriple(TT);
   assert((TheTriple.isOSBinFormatELF() || TheTriple.isOSBinFormatMachO()) &&
          "Only expect Darwin and ELF targets");