Added the missing bit definition for the 4th bit of the STR (post reg) instruction...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 3af0d3fc327eb095a6d563f45b67b8b4acd9d298..c8966fb97a4c9d67d5c9cb154069250f13e4e73b 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -827,6 +827,8 @@ class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
   let Inst{7-4}   = 0b0111;
   let Inst{9-8}   = 0b00;
   let Inst{27-20} = opcod;
+
+  let Unpredictable{9-8} = 0b11;
 }
 
 // Misc Arithmetic instructions.

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 633b53fefc935652a46ca6de98eadd63abe0e638..e89c2312fe6163e51ce64b32f936d1ead6d1f778 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1614,6 +1614,8 @@ def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
   let Inst{27-20} = 0b01101000;
   let Inst{7-4} = 0b1011;
   let Inst{11-8} = 0b1111;
+  
+  let Unpredictable{11-8} = 0b1111;
 }
 
 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
@@ -2429,6 +2431,7 @@ multiclass AI2_stridx<bit isByte, string opc,
      let Inst{23} = offset{12};
      let Inst{19-16} = addr;
      let Inst{11-0} = offset{11-0};
+     let Inst{4} = 0;
 
     let DecoderMethod = "DecodeAddrMode2IdxInstruction";
    }

diff --git a/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt
new file mode 100644 (file)
index 0000000..6f1da8e
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt
@@ -0,0 +1,62 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s -check-prefix=CHECK-WARN
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x03 0xaf 0x06
+# CHECK: sxtb
+0x74 0x03 0xaf 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xbf 0x06
+# CHECK: sxth
+0x74 0x3f 0xbf 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xa6 0x06
+# CHECK: sxtab
+0x74 0x3f 0xa6 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xb7 0x06
+# CHECK: sxtah
+0x74 0x3f 0xb7 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0x8f 0x06
+# CHECK: sxtb16
+0x74 0x3f 0x8f 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0x86 0x06
+# CHECK: sxtab16
+0x74 0x3f 0x86 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xef 0x06
+# CHECK: uxtb
+0x74 0x3f 0xef 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xff 0x06
+# CHECK: uxth
+0x74 0x3f 0xff 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xcf 0x06
+# CHECK: uxtb16
+0x74 0x3f 0xcf 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xe4 0x06
+# CHECK: uxtab
+0x74 0x3f 0xe4 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xf2 0x06
+# CHECK: uxtah
+0x74 0x3f 0xf2 0x06
+
+# CHECK-WARN: potentially undefined
+# CHECK-WARN: 0x74 0x3f 0xc4 0x06
+# CHECK: uxtab16
+0x74 0x3f 0xc4 0x06

diff --git a/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt
new file mode 100644 (file)
index 0000000..d7939c1
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0xb4 0x38 0x80 0x06
+0xb4 0x38 0x80 0x06