outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
}
// These two could be merge in with the above, but their patterns aren't really
(ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
outs,
(ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
[/* No Pattern: same as uxtx */],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
}
multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
- outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [/* No pattern: probably same as uxtw */],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ outs,
+ (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [/* No pattern: probably same as uxtw */],
+ NoItinerary>;
def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
- outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [/* No Pattern: probably same as uxtw */],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ outs,
+ (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [/* No Pattern: probably same as uxtw */],
+ NoItinerary>;
}
class SetRD<RegisterClass RC, SDPatternOperator op>
(ins GPRsp:$Rn, imm_operand:$Imm12),
!strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
[(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
// S variants can read SP but would write to ZR
(ins GPRsp:$Rn, imm_operand:$Imm12),
!strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
[(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
let Defs = [NZCV];
}
!strconcat(cmpasmop, " $Rn, $Imm12"),
[(set NZCV,
(A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
let Rd = 0b11111;
let Defs = [NZCV];
let isCompare = 1;
// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
//===-------------------------------
-// 1. The "shifted register" operands. Shared with logical insts.
+// 1. The "shifed register" operands. Shared with logical insts.
//===-------------------------------
multiclass shift_operands<string prefix, string form> {
[(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
def _lsr : A64I_addsubshift<sf, op, s, 0b01,
(outs GPR:$Rd),
[(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
!cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
def _asr : A64I_addsubshift<sf, op, s, 0b10,
(outs GPR:$Rd),
[(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
!cast<Operand>("asr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
}
def _noshift
[(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteCMP, ReadCMP, ReadCMP]>;
+ NoItinerary>;
def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
(outs),
[(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
!cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteCMP, ReadCMP, ReadCMP]>;
+ NoItinerary>;
def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
(outs),
[(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
!cast<Operand>("asr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteCMP, ReadCMP, ReadCMP]>;
+ NoItinerary>;
}
def _noshift
def www : A64I_addsubcarry<0b0, op, s, 0b000000,
(outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ [], NoItinerary>;
def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ [], NoItinerary>;
}
}
def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
(ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
}
def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
(ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
}
}
def BFMwwii :
A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
- "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
def BFMxxii :
A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
- "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
: A64I_bitfield<sf, opc, sf,
(outs GPRDest:$Rd), (ins GPR32:$Rn),
!strconcat(asmop, "\t$Rd, $Rn"),
- [(set dty:$Rd, pattern)], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ [(set dty:$Rd, pattern)], NoItinerary> {
let ImmR = 0b000000;
let ImmS = imms;
}
(outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
[(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
let ImmS = 31;
}
(outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
[(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
let ImmS = 63;
}
: A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
"lsl\t$Rd, $Rn, $FullImm",
[(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
bits<12> FullImm;
let ImmR = FullImm{5-0};
let ImmS = FullImm{11-6};
(ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
[(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
(ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
[(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
// Again, variants based on BFM modify Rd so need it as an input too.
def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
- (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
- "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
+ "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
}
def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
- (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
- "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
+ "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
(ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
(ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
- "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
- "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
- Sched<[WriteALU, ReadALU]> {
+ "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
(ins GPR64:$Rt, bcc_target:$Label),
!strconcat(asmop,"\t$Rt, $Label"),
[(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr, ReadBr]>;
+ NoItinerary>;
def w : A64I_cmpbr<0b0, op,
(outs),
(ins GPR32:$Rt, bcc_target:$Label),
!strconcat(asmop,"\t$Rt, $Label"),
[(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr, ReadBr]>;
+ NoItinerary>;
}
}
def Bcc : A64I_condbr<0b0, 0b0, (outs),
(ins cond_code:$Cond, bcc_target:$Label),
"b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr]> {
+ NoItinerary> {
let Uses = [NZCV];
let isBranch = 1;
let isTerminator = 1;
: A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
(ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
- [], NoItinerary>,
- Sched<[WriteCMP, ReadCMP]> {
+ [], NoItinerary> {
let Defs = [NZCV];
}
(ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
[(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
- NoItinerary>,
- Sched<[WriteCMP, ReadCMP]>;
+ NoItinerary>;
def xxxc : A64I_condsel<0b1, op, 0b0, op2,
(ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
[(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
- NoItinerary>,
- Sched<[WriteCMP, ReadCMP]>;
+ NoItinerary>;
}
}
(outs GPRrc:$Rd),
(ins GPRrc:$Rn),
patterns,
- itin>,
- Sched<[WriteALU, ReadALU]>;
+ itin>;
multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
let hasSideEffects = 0 in {
(outs GPRsp:$Rd),
(ins GPRsp:$Rn, GPRsp:$Rm),
patterns,
- itin>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ itin>;
multiclass dp_2src_crc<bit c, string asmop> {
def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
defm CRC32 : dp_2src_crc<0b0, "crc32">;
defm CRC32C : dp_2src_crc<0b1, "crc32c">;
-let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {
- defm UDIV : dp_2src<0b000010, "udiv", udiv>;
- defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
-}
+defm UDIV : dp_2src<0b000010, "udiv", udiv>;
+defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
-let SchedRW = [WriteALUs, ReadALU, ReadALU] in {
- defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
- defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
- defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
- defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
-}
+defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
+defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
+defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
+defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
// Extra patterns for an incoming 64-bit value for a 32-bit
// operation. Since the LLVM operations are undefined (as in C) if the
: A64I_dp3<sf, opcode,
(outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
- [(set AccTy:$Rd, pattern)], NoItinerary>,
- Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
+ [(set AccTy:$Rd, pattern)], NoItinerary> {
RegisterClass AccGPR = AccReg;
RegisterClass SrcGPR = SrcReg;
}
(ins GPR64:$Rn, GPR64:$Rm),
"umulh\t$Rd, $Rn, $Rm",
[(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
- NoItinerary>,
- Sched<[WriteMAC, ReadMAC, ReadMAC]>;
+ NoItinerary>;
def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm),
"smulh\t$Rd, $Rn, $Rm",
[(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
- NoItinerary>,
- Sched<[WriteMAC, ReadMAC, ReadMAC]>;
+ NoItinerary>;
}
multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
: A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
- !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,
- Sched<[WriteBr]> {
+ !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
let isBranch = 1;
let isTerminator = 1;
}
"extr\t$Rd, $Rn, $Rm, $LSB",
[(set i32:$Rd,
(A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
(outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
"extr\t$Rd, $Rn, $Rm, $LSB",
[(set i64:$Rd,
(A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def : InstAlias<"ror $Rd, $Rs, $LSB",
(EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
(outs), ins, "fcmp\t$Rn, $Rm", [pattern],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
+ NoItinerary> {
let Defs = [NZCV];
}
def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
- (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
+ (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
let Defs = [NZCV];
}
}
(outs),
(ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
- [], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
+ [], NoItinerary> {
let Defs = [NZCV];
}
def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
(ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
"fcsel\t$Rd, $Rn, $Rm, $Cond",
- [(set f32:$Rd,
+ [(set f32:$Rd,
(simple_select f32:$Rn, f32:$Rm))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
+ NoItinerary>;
def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
"fcsel\t$Rd, $Rn, $Rm, $Cond",
[(set f64:$Rd,
(simple_select f64:$Rn, f64:$Rm))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
+ NoItinerary>;
}
//===----------------------------------------------------------------------===//
def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
!strconcat(asmstr, "\t$Rd, $Rn"),
[(set f32:$Rd, (opnode f32:$Rn))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ NoItinerary>;
def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
!strconcat(asmstr, "\t$Rd, $Rn"),
[(set f64:$Rd, (opnode f64:$Rn))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ NoItinerary>;
}
defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
-let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
- defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
-}
+defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
{0,0,0,1, DestReg.t1, DestReg.t0},
(outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
"fcvt\t$Rd, $Rn",
- [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
(ins FPR32:$Rn, FPR32:$Rm),
!strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
[(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
+ NoItinerary>;
def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
(outs FPR64:$Rd),
(ins FPR64:$Rn, FPR64:$Rm),
!strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
[(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
+ NoItinerary>;
}
let isCommutable = 1 in {
- let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
- defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
- }
+ defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
// No patterns for these.
defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
- let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
- defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
- PatFrag<(ops node:$lhs, node:$rhs),
- (fneg (fmul node:$lhs, node:$rhs))> >;
- }
+ defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
+ PatFrag<(ops node:$lhs, node:$rhs),
+ (fneg (fmul node:$lhs, node:$rhs))> >;
}
-let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
- defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
-}
+defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
//===----------------------------------------------------------------------===//
(ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
!strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
[(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
- NoItinerary>,
- Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;
+ NoItinerary>;
def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
// worth going for a multiclass here. Oh well.
class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
- RegisterClass GPR, RegisterClass FPR,
- ValueType DstTy, ValueType SrcTy,
+ RegisterClass GPR, RegisterClass FPR,
+ ValueType DstTy, ValueType SrcTy,
Operand scale_op, string asmop, SDNode cvtop>
: A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
(outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
!strconcat(asmop, "\t$Rd, $Rn, $Scale"),
[(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ NoItinerary>;
def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
(outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
!strconcat(asmop, "\t$Rd, $Rn, $Scale"),
[(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
- NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ NoItinerary>;
def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
RegisterClass DestPR, RegisterClass SrcPR, string asmop>
: A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
- !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
let DecoderMethod = "DecodeFMOVLaneInstruction" in {
def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
(outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
- "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
(outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
- "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,
- Sched<[WriteFPALU, ReadFPALU]>;
+ "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
}
let Predicates = [HasFPARMv8] in {
(ins fmov_operand:$Imm8),
"fmov\t$Rd, $Imm8",
[(set VT:$Rd, fmov_operand:$Imm8)],
- NoItinerary>,
- Sched<[WriteFPALU]>;
+ NoItinerary>;
def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
list<dag> patterns = []>
: A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
- "ldr\t$Rt, $Imm19", patterns, NoItinerary>,
- Sched<[WriteLd]>;
+ "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
let mayLoad = 1 in {
def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
(outs GPR64:$Rt),
(ins ldrlit_label:$Imm19),
"ldrsw\t$Rt, $Imm19",
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
def PRFM_lit : A64I_LDRlit<0b11, 0b0,
(outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
"prfm\t$Rt, $Imm19",
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
}
//===----------------------------------------------------------------------===//
multiclass A64I_LRex<string asmstr, bits<3> opcode> {
def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
(outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
(outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
(outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
(outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
}
defm LDXR : A64I_LRex<"ldxr", 0b000>;
def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
(outs GPR32:$Rt, GPR32:$Rt2),
(ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
(outs GPR64:$Rt, GPR64:$Rt2),
(ins GPR64xsp0:$Rn),
- [], NoItinerary>,
- Sched<[WriteLd]>;
+ [], NoItinerary>;
}
defm LDXP : A64I_LPex<"ldxp", 0b010>;
def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
(outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
(outs GPR:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
(outs GPR:$Rt),
(ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
}
def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
(!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
(outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
"ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
(outs GPR:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
}
def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
(!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]>;
+ [], NoItinerary>;
def x_U : A64I_LSunalimm<size, 0b0, 0b10,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]>;
+ [], NoItinerary>;
// Post-indexed
(outs GPR32:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR32:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, word_uimm12:$UImm12),
"ldrsw\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
"ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
"ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd, ReadLd]>;
+ [], NoItinerary>;
}
def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
(LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldursw\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
"prfm\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>,
- Sched<[WritePreLd, ReadPreLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"prfm $Rt, [$Rn]",
(ins prefetch_op:$Rt, GPR64xsp:$Rn,
GPR32:$Rm, dword_Wm_regext:$Ext),
"prfm\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WritePreLd, ReadPreLd]>;
+ [], NoItinerary>;
def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn,
GPR64:$Rm, dword_Xm_regext:$Ext),
"prfm\t$Rt, [$Rn, $Rm, $Ext]",
- [], NoItinerary>,
- Sched<[WritePreLd, ReadPreLd]>;
+ [], NoItinerary>;
}
def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"prfum\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WritePreLd, ReadPreLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"prfum $Rt, [$Rn]",
def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayStore = 1;
}
def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
(outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]>;
+ [], NoItinerary>;
def x : A64I_LSunpriv<size, 0b0, 0b10,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]>;
+ [], NoItinerary>;
}
def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtrsw\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
Operand simm7, string prefix> {
def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
- "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayStore = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def _LDR : A64I_LSPoffset<opc, v, 0b1,
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
- "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
- "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
(outs GPR64:$Rt, GPR64:$Rt2),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
- "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary>,
- Sched<[WriteLd, ReadLd]> {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
[(set i32:$Rd,
(opnode i32:$Rn, logical_imm32_operand:$Imm))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
(ins GPR64:$Rn, logical_imm64_operand:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
[(set i64:$Rd,
(opnode i64:$Rn, logical_imm64_operand:$Imm))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ NoItinerary>;
}
defm AND : A64I_logimmSizes<0b00, "and", and>;
def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
(ins GPR32:$Rn, logical_imm32_operand:$Imm),
"ands\t$Rd, $Rn, $Imm",
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ [], NoItinerary>;
def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
(ins GPR64:$Rn, logical_imm64_operand:$Imm),
"ands\t$Rd, $Rn, $Imm",
- [], NoItinerary>,
- Sched<[WriteALU, ReadALU]>;
+ [], NoItinerary>;
}
[(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
(outs GPR:$Rd),
[(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
!cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _asr : A64I_logicalshift<sf, opc, 0b10, N,
(outs GPR:$Rd),
[(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
!cast<Operand>("asr_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _ror : A64I_logicalshift<sf, opc, 0b11, N,
(outs GPR:$Rd),
[(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
!cast<Operand>("ror_operand_" # ty):$Imm6))
)],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
}
def _noshift
[(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6)),
0, signed_cond))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
[(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
!cast<Operand>("lsr_operand_" # ty):$Imm6)),
0, signed_cond))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
(outs),
[(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
!cast<Operand>("asr_operand_" # ty):$Imm6)),
0, signed_cond))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
(outs),
[(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
!cast<Operand>("ror_operand_" # ty):$Imm6)),
0, signed_cond))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
}
def _noshift : InstAlias<"tst $Rn, $Rm",
"mvn\t$Rd, $Rm, $Imm6",
[(set ty:$Rd, (not (shl ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6)))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
"mvn\t$Rd, $Rm, $Imm6",
[(set ty:$Rd, (not (srl ty:$Rm,
!cast<Operand>("lsr_operand_" # ty):$Imm6)))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
(outs GPR:$Rd),
"mvn\t$Rd, $Rm, $Imm6",
[(set ty:$Rd, (not (sra ty:$Rm,
!cast<Operand>("asr_operand_" # ty):$Imm6)))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
(outs GPR:$Rd),
"mvn\t$Rd, $Rm, $Imm6",
[(set ty:$Rd, (not (rotr ty:$Rm,
!cast<Operand>("lsl_operand_" # ty):$Imm6)))],
- NoItinerary>,
- Sched<[WriteALU, ReadALU, ReadALU]>;
+ NoItinerary>;
}
def _noshift : InstAlias<"mvn $Rn, $Rm",
def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
!strconcat(asmop, "\t$Rd, $FullImm"),
- [], NoItinerary>,
- Sched<[WriteALU]> {
+ [], NoItinerary> {
bits<18> FullImm;
let UImm16 = FullImm{15-0};
let Shift = FullImm{17-16};
def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
!strconcat(asmop, "\t$Rd, $FullImm"),
- [], NoItinerary>,
- Sched<[WriteALU]> {
+ [], NoItinerary> {
bits<18> FullImm;
let UImm16 = FullImm{15-0};
let Shift = FullImm{17-16};
let hasSideEffects = 0 in {
def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
- "adr\t$Rd, $Label", [], NoItinerary>,
- Sched<[WriteALUs]>;
+ "adr\t$Rd, $Label", [], NoItinerary>;
def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
- "adrp\t$Rd, $Label", [], NoItinerary>,
- Sched<[WriteALUs]>;
+ "adrp\t$Rd, $Label", [], NoItinerary>;
}
//===----------------------------------------------------------------------===//
"tbz\t$Rt, $Imm, $Label",
[(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
A64eq, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr]>;
+ NoItinerary>;
def TBNZxii : A64I_TBimm<0b1, (outs),
(ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
"tbnz\t$Rt, $Imm, $Label",
[(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
A64ne, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr]>;
+ NoItinerary>;
// Note, these instructions overlap with the above 64-bit patterns. This is
"tbz\t$Rt, $Imm, $Label",
[(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
A64eq, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr]> {
+ NoItinerary> {
let Imm{5} = 0b0;
}
"tbnz\t$Rt, $Imm, $Label",
[(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
A64ne, bb:$Label)],
- NoItinerary>,
- Sched<[WriteBr]> {
+ NoItinerary> {
let Imm{5} = 0b0;
}
}
class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
: A64I_Bimm<op, (outs), (ins lbl_type:$Label),
!strconcat(asmop, "\t$Label"), patterns,
- NoItinerary>,
- Sched<[WriteBr]>;
+ NoItinerary>;
let isBranch = 1 in {
def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
let isBarrier = 1;
}
- let SchedRW = [WriteBrL] in {
- def BLimm : A64I_BimmImpl<0b1, "bl",
- [(AArch64Call tglobaladdr:$Label)], blimm_target> {
- let isCall = 1;
- let Defs = [X30];
- }
+ def BLimm : A64I_BimmImpl<0b1, "bl",
+ [(AArch64Call tglobaladdr:$Label)], blimm_target> {
+ let isCall = 1;
+ let Defs = [X30];
}
}
dag outs, dag ins, string asmstr, list<dag> patterns,
InstrItinClass itin = NoItinerary>
: A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
- outs, ins, asmstr, patterns, itin>,
- Sched<[WriteBr]> {
+ outs, ins, asmstr, patterns, itin> {
let isBranch = 1;
let isIndirectBranch = 1;
}
let isTerminator = 1;
}
- let SchedRW = [WriteBrL] in {
- def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
- "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
- let isBarrier = 0;
- let isCall = 1;
- let Defs = [X30];
- }
+ def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
+ "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
+ let isBarrier = 0;
+ let isCall = 1;
+ let Defs = [X30];
}
def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
projects / oota-llvm.git / commitdiff