[AArch64] AsmParser should be case insensitive about accepting vector register names.
authorRanjeet Singh <Ranjeet.Singh@arm.com>
Mon, 8 Jun 2015 21:32:16 +0000 (21:32 +0000)
committerRanjeet Singh <Ranjeet.Singh@arm.com>
Mon, 8 Jun 2015 21:32:16 +0000 (21:32 +0000)
Differential Revision: http://reviews.llvm.org/D10320

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239353 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
test/MC/AArch64/case-insen-reg-names.s [new file with mode: 0644]

index 41615b6ede0882c650238593dc64c2644b468d66..063c053ffe8aede79384350acdc3a8465933335f 100644 (file)
@@ -1764,7 +1764,7 @@ static unsigned MatchRegisterName(StringRef Name);
 /// }
 
 static unsigned matchVectorRegName(StringRef Name) {
-  return StringSwitch<unsigned>(Name)
+  return StringSwitch<unsigned>(Name.lower())
       .Case("v0", AArch64::Q0)
       .Case("v1", AArch64::Q1)
       .Case("v2", AArch64::Q2)
diff --git a/test/MC/AArch64/case-insen-reg-names.s b/test/MC/AArch64/case-insen-reg-names.s
new file mode 100644 (file)
index 0000000..b31ab67
--- /dev/null
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
+fadd v0.2d, v5.2d, v6.2d
+fadd V0.2d, V5.2d, V6.2d
+fadd v0.2d, V5.2d, v6.2d
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]