ARM simplify the postidx_reg operand encoding.

The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index dcc86957ade24b1e6b40e310652b8f33e2c87562..6837d3622c3899c0492baab3741b47bf97aca9dc 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1093,8 +1093,7 @@ void ARMOperand::print(raw_ostream &OS) const {
     OS << ">";
     break;
   case PostIndexRegister:
-    OS << "post-idx register " 
-       << getAddrOpcStr(ARM_AM::getAM3Op(PostIdxReg.Imm))
+    OS << "post-idx register " << (PostIdxReg.Imm ? "" : "-")
        << PostIdxReg.RegNum
        << ">";
     break;
@@ -1872,14 +1871,14 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   AsmToken Tok = Parser.getTok();
   SMLoc S = Tok.getLoc();
   bool haveEaten = false;
-  unsigned Imm = ARM_AM::getAM3Opc(ARM_AM::add, 0);
+  bool isAdd = true;
   int Reg = -1;
   if (Tok.is(AsmToken::Plus)) {
     Parser.Lex(); // Eat the '+' token.
     haveEaten = true;
   } else if (Tok.is(AsmToken::Minus)) {
     Parser.Lex(); // Eat the '-' token.
-    Imm = ARM_AM::getAM3Opc(ARM_AM::sub, 0);
+    isAdd = false;
     haveEaten = true;
   }
   if (Parser.getTok().is(AsmToken::Identifier))
@@ -1892,7 +1891,7 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   }
   SMLoc E = Parser.getTok().getLoc();
 
-  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, Imm, S, E));
+  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, S, E));
 
   return MatchOperand_Success;
 }

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 26716763cf4caca1078f4f78a0bcd58e0a687192..d460ecd694c1707b6c1088431f44f68175493189 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1543,10 +1543,16 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
     ++OpIdx;
   } else {
     // Disassemble the offset reg (Rm).
-    unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRm(insn))));
-    MI.addOperand(MCOperand::CreateImm(Offset));
+    // FIXME: Remove the 'else' once done w/ addrmode3 refactor.
+    if (Opcode == ARM::STRHTr || Opcode == ARM::LDRSBTr ||
+        Opcode == ARM::LDRHTr || Opcode == ARM::LDRSHTr)
+      MI.addOperand(MCOperand::CreateImm(getUBit(insn)));
+    else {
+      unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
+      MI.addOperand(MCOperand::CreateImm(Offset));
+    }
     OpIdx += 2;
   }
 

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 7972b27290f310f660cdfeda7650634237fd609d..ef4069913407c8a2b8704b4ea33db5cbcd2ceb43 100644 (file)
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -387,8 +387,7 @@ void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
   const MCOperand &MO1 = MI->getOperand(OpNum);
   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 
-  O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
-    << getRegisterName(MO1.getReg());
+  O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
 }
 
 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,

diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index c66941613c63a7991d86116e263226717355f354..2caf548f888e1b583c555869cec83d37df2b0456 100644 (file)
--- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -812,8 +812,7 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
   // {3-0}    Rm
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
-  unsigned Imm = MO1.getImm();
-  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
+  bool isAdd = MO1.getImm() != 0;
   return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
 }