Don't force promotion of return arguments on the callee.

Some architectures (like x86) don't require it.
This fixes bug 3779.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 855f9a443b757aaefae12542dd9a28b1e21ca969..0e8d9bee5ed1216dc0598201c9cf397e03099665 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -979,15 +979,6 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
     for (unsigned j = 0, f = NumValues; j != f; ++j) {
       MVT VT = ValueVTs[j];
 
-      // FIXME: C calling convention requires the return type to be promoted to
-      // at least 32-bit. But this is not necessary for non-C calling
-      // conventions.
-      if (VT.isInteger()) {
-        MVT MinVT = TLI.getRegisterType(MVT::i32);
-        if (VT.bitsLT(MinVT))
-          VT = MinVT;
-      }
-
       unsigned NumParts = TLI.getNumRegisters(VT);
       MVT PartVT = TLI.getRegisterType(VT);
       SmallVector<SDValue, 4> Parts(NumParts);

diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll
index a18b6f8d05fc46566fcc20670f34375dca3fc055..cb066963b17175741bbeb4fc21de3846456ddd09 100644 (file)
--- a/test/CodeGen/CellSPU/and_ops.ll
+++ b/test/CodeGen/CellSPU/and_ops.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep and    %t1.s | count 234
+; RUN: grep and    %t1.s | count 230
 ; RUN: grep andc   %t1.s | count 85
-; RUN: grep andi   %t1.s | count 37
+; RUN: grep andi   %t1.s | count 35
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 

diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll
index 540695677205f09dc43ba920047a493d2efe9664..a578315c6b045a324de743968346090829084764 100644 (file)
--- a/test/CodeGen/CellSPU/eqv.ll
+++ b/test/CodeGen/CellSPU/eqv.ll
@@ -1,8 +1,5 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep eqv  %t1.s | count 18
-; RUN: grep xshw %t1.s | count 6
-; RUN: grep xsbh %t1.s | count 3
-; RUN: grep andi %t1.s | count 3
 
 ; Test the 'eqv' instruction, whose boolean expression is:
 ; (a & b) | (~a & ~b), which simplifies to

diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll
index 16bf0f9f62ad30aeffb648e016940dae22c996d7..56d1b8fb41b2ee72c5963c556bd89bf392e4a629 100644 (file)
--- a/test/CodeGen/CellSPU/icmp16.ll
+++ b/test/CodeGen/CellSPU/icmp16.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep ilh                                %t1.s | count 5
+; RUN: grep ilh                                %t1.s | count 15
 ; RUN: grep ceqh                               %t1.s | count 29
 ; RUN: grep ceqhi                              %t1.s | count 13
 ; RUN: grep clgth                              %t1.s | count 15

diff --git a/test/CodeGen/CellSPU/immed16.ll b/test/CodeGen/CellSPU/immed16.ll
index 684305bd0c97842f7ce25bcae047a4414c936f3c..9a461cbb85a615d628dd4fc119ffdebe92c8f5cd 100644 (file)
--- a/test/CodeGen/CellSPU/immed16.ll
+++ b/test/CodeGen/CellSPU/immed16.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep "ilh" %t1.s | count 5
+; RUN: grep "ilh" %t1.s | count 11
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll
index 841a3ec54d6f23085a21e36bbfde093c77ea9e1f..ccbd5d90e54ae1f65c9f3698be36cc70c810aba4 100644 (file)
--- a/test/CodeGen/CellSPU/nand.ll
+++ b/test/CodeGen/CellSPU/nand.ll
@@ -1,8 +1,6 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep nand   %t1.s | count 90
-; RUN: grep and    %t1.s | count 94
-; RUN: grep xsbh   %t1.s | count 2
-; RUN: grep xshw   %t1.s | count 4
+; RUN: grep and    %t1.s | count 90
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll
index 4e9da8f1297224faee3919001f06d6f771ec218f..49e5ec36d28814a643e9361d6f68c583926b429c 100644 (file)
--- a/test/CodeGen/CellSPU/or_ops.ll
+++ b/test/CodeGen/CellSPU/or_ops.ll
@@ -1,5 +1,4 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep and    %t1.s | count 2
 ; RUN: grep orc    %t1.s | count 85
 ; RUN: grep ori    %t1.s | count 30
 ; RUN: grep orhi   %t1.s | count 30

diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 3c26baa7c7ab705d5a0db162a6ca5010f369e0b1..3b7dacd3cd762e3bef2aef22074d333c502b0918 100644 (file)
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -3,8 +3,6 @@
 ; RUN: grep {shlhi     }  %t1.s | count 3
 ; RUN: grep {shl       }  %t1.s | count 9
 ; RUN: grep {shli      }  %t1.s | count 3
-; RUN: grep {xshw      }  %t1.s | count 5
-; RUN: grep {and       }  %t1.s | count 5
 ; RUN: grep {andi      }  %t1.s | count 2
 ; RUN: grep {rotmi     }  %t1.s | count 2
 ; RUN: grep {rotqmbyi  }  %t1.s | count 1

diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
index f2f35ef4dbc45d565eb81fd7434fe63ea1c07eea..f59bfd49acf2d4ba6a8d180c5edb584ddc83fcaf 100644 (file)
--- a/test/CodeGen/CellSPU/stores.ll
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -6,13 +6,13 @@
 ; RUN: grep 771                 %t1.s | count 4
 ; RUN: grep 515                 %t1.s | count 2
 ; RUN: grep 1799                %t1.s | count 2
-; RUN: grep 1543                %t1.s | count 5
-; RUN: grep 1029                %t1.s | count 3
+; RUN: grep 1543                %t1.s | count 3
+; RUN: grep 1029                %t1.s | count 1
 ; RUN: grep {shli.*, 4}         %t1.s | count 4
 ; RUN: grep stqx                %t1.s | count 4
-; RUN: grep ilhu                %t1.s | count 11
-; RUN: grep iohl                %t1.s | count 8
-; RUN: grep shufb               %t1.s | count 15
+; RUN: grep ilhu                %t1.s | count 9
+; RUN: grep iohl                %t1.s | count 6
+; RUN: grep shufb               %t1.s | count 13
 ; RUN: grep frds                %t1.s | count 1
 
 ; ModuleID = 'stores.bc'

diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
index 82d319dd1050b859f031d25bf1808c97d5d86867..260a7f41989940858e2028b6a611d78512364d77 100644 (file)
--- a/test/CodeGen/CellSPU/struct_1.ll
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -3,8 +3,6 @@
 ; RUN: grep lqa     %t1.s | count 5
 ; RUN: grep lqd     %t1.s | count 11
 ; RUN: grep rotqbyi %t1.s | count 7
-; RUN: grep xshw    %t1.s | count 1
-; RUN: grep andi    %t1.s | count 5
 ; RUN: grep cbd     %t1.s | count 3
 ; RUN: grep chd     %t1.s | count 1
 ; RUN: grep cwd     %t1.s | count 3
@@ -14,8 +12,6 @@
 ; RUN: grep ilhu    %t2.s | count 16
 ; RUN: grep lqd     %t2.s | count 16
 ; RUN: grep rotqbyi %t2.s | count 7
-; RUN: grep xshw    %t2.s | count 1
-; RUN: grep andi    %t2.s | count 5
 ; RUN: grep cbd     %t2.s | count 3
 ; RUN: grep chd     %t2.s | count 1
 ; RUN: grep cwd     %t2.s | count 3

diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
index b62d2c61bba7af9d0089e296a7bb9def9fa729a2..ffb1e83a276d35a1c6b08087b32dafea576d99cc 100644 (file)
--- a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
+++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl}
+; RUN: llvm-as < %s | llc -march=x86 | not grep {movsbl}
 
 @X = global i32 0               ; <i32*> [#uses=1]
 

diff --git a/test/CodeGen/X86/20090313-signext.ll b/test/CodeGen/X86/20090313-signext.ll
new file mode 100644 (file)
index 0000000..d41b245
--- /dev/null
+++ b/test/CodeGen/X86/20090313-signext.ll
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep {movswl    %ax, %edi} %t
+; RUN: grep {movw      x(%rip), %ax} %t
+
+@x = common global i16 0
+
+define signext i16 @f() nounwind {
+entry:
+       %0 = tail call signext i16 @h() nounwind
+       %1 = sext i16 %0 to i32
+       tail call void @g(i32 %1) nounwind
+       %2 = load i16* @x, align 2
+       ret i16 %2
+}
+
+declare signext i16 @h()
+
+declare void @g(i32)

diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll
index 6e3156beb0f61409702bbaa7bd8d7883046753c6..8cdf4ac22d92a7f54260af8bad7b14875922b0b2 100644 (file)
--- a/test/CodeGen/X86/const-select.ll
+++ b/test/CodeGen/X86/const-select.ll
@@ -10,7 +10,7 @@ entry:
        ret float %iftmp.0.0
 }
 
-; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax}
+; RUN: llvm-as < %s | llc | grep {movb.*(%e.x,%e.x,4), %al}
 define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
 entry:
        %0 = fcmp olt double %F, 4.200000e+01           ; <i1> [#uses=1]

diff --git a/test/CodeGen/X86/isel-sink2.ll b/test/CodeGen/X86/isel-sink2.ll
index d8e27e9aff6025034a6257812d9bd10d56df25cb..9d9c747fa49599477e7d5b96ef308d94bf85664a 100644 (file)
--- a/test/CodeGen/X86/isel-sink2.ll
+++ b/test/CodeGen/X86/isel-sink2.ll
@@ -1,5 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {movzbl.7(%...)}
-; RUN: llvm-as < %s | llc -march=x86 | not grep leal
+; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: grep {movb.7(%...)} %t
+; RUN: not grep leal %t
 
 define i8 @test(i32 *%P) nounwind {
   %Q = getelementptr i32* %P, i32 1

diff --git a/test/CodeGen/X86/sext-trunc.ll b/test/CodeGen/X86/sext-trunc.ll
index 97b46668270239563417daa14070f566b2cc5104..df401564c24f91e28673bb0f1acb2a016c2b631c 100644 (file)
--- a/test/CodeGen/X86/sext-trunc.ll
+++ b/test/CodeGen/X86/sext-trunc.ll
@@ -1,5 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 > %t
-; RUN: grep movsbl %t
+; RUN: grep movb %t
+; RUN: not grep movsbl %t
 ; RUN: not grep movz %t
 ; RUN: not grep and %t
 

diff --git a/test/CodeGen/X86/tls11.ll b/test/CodeGen/X86/tls11.ll
index 32d0a1204ca7d54019e3d7c9c681c306c8ac3560..f8543c089f2cd119a94c9429c4439817e92e2c56 100644 (file)
--- a/test/CodeGen/X86/tls11.ll
+++ b/test/CodeGen/X86/tls11.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movzwl    %gs:i@NTPOFF, %eax} %t
+; RUN: grep {movw      %gs:i@NTPOFF, %ax} %t
 
 @i = thread_local global i16 15
 

diff --git a/test/CodeGen/X86/tls12.ll b/test/CodeGen/X86/tls12.ll
index c6f766d4472c2b4fa7910f4c87a3442850b772bc..17ea996aa455996cfab09dad7644b7e805d3b909 100644 (file)
--- a/test/CodeGen/X86/tls12.ll
+++ b/test/CodeGen/X86/tls12.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movzbl    %gs:i@NTPOFF, %eax} %t
+; RUN: grep {movb      %gs:i@NTPOFF, %al} %t
 
 @i = thread_local global i8 15