Fix encoding of Thumb2 shifted register operands with RRX shifts.
authorOwen Anderson <resistor@mac.com>
Tue, 13 Sep 2011 17:34:32 +0000 (17:34 +0000)
committerOwen Anderson <resistor@mac.com>
Tue, 13 Sep 2011 17:34:32 +0000 (17:34 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
test/MC/ARM/basic-thumb2-instructions.s

index 9117d65dbc2008778e8204820a9128ed6ae3ea55..865c3e22b8424f3899a038686c5afa98950390a9 100644 (file)
@@ -1277,6 +1277,7 @@ getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
   case ARM_AM::lsl: SBits = 0x0; break;
   case ARM_AM::lsr: SBits = 0x2; break;
   case ARM_AM::asr: SBits = 0x4; break;
+  case ARM_AM::rrx: // FALLTHROUGH
   case ARM_AM::ror: SBits = 0x6; break;
   }
 
index d7df77735bcb671d9e8c66bf8f6aaadaa4081322..8293d4c01c81fa2dc283b43ef91fe57079626276 100644 (file)
@@ -1029,3 +1029,11 @@ _func:
 @ CHECK: nopne                          @ encoding: [0x00,0xbf]
 @ CHECK: subne r5, r6, r7              @ encoding: [0xf5,0x1b]
 @ CHECK: addeq r1, r2, #4              @ encoding: [0x11,0x1d]
+
+@------------------------------------------------------------------------------
+@ SUB (register)
+@------------------------------------------------------------------------------
+        sub.w r5, r2, r12, rrx
+
+@ CHECK: sub.w r5, r2, r12, rrx        @ encoding: [0xa2,0xeb,0x3c,0x05]
+